/**Function*************************************************************
Synopsis [Derive truth table for each cofactor.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int If_ManCutTruthCheck_rec( If_Obj_t * pObj, word * pTruths )
{
word T0, T1;
if ( pObj->fMark )
return pTruths[If_ObjId(pObj)];
assert( If_ObjIsAnd(pObj) );
T0 = If_ManCutTruthCheck_rec( If_ObjFanin0(pObj), pTruths );
T1 = If_ManCutTruthCheck_rec( If_ObjFanin1(pObj), pTruths );
T0 = If_ObjFaninC0(pObj) ? ~T0 : T0;
T1 = If_ObjFaninC1(pObj) ? ~T1 : T1;
return T0 & T1;
}
/**Function*************************************************************
Synopsis [Interface with the FPGA mapping package.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void If_ManComputeSwitching( If_Man_t * pIfMan )
{
abctime clk = Abc_Clock();
Gia_Man_t * pNew;
Vec_Int_t * vCopy;
If_Obj_t * pIfObj;
int i;
assert( pIfMan->vSwitching == NULL );
// create the new manager
pNew = Gia_ManStart( If_ManObjNum(pIfMan) );
vCopy = Vec_IntAlloc( If_ManObjNum(pIfMan) );
// constant and inputs
Vec_IntPush( vCopy, 1 );
If_ManForEachCi( pIfMan, pIfObj, i )
Vec_IntPush( vCopy, Gia_ManAppendCi(pNew) );
// internal nodes
If_ManForEachNode( pIfMan, pIfObj, i )
{
int iLit0 = Abc_LitNotCond( Vec_IntEntry(vCopy, If_ObjFanin0(pIfObj)->Id), If_ObjFaninC0(pIfObj) );
int iLit1 = Abc_LitNotCond( Vec_IntEntry(vCopy, If_ObjFanin1(pIfObj)->Id), If_ObjFaninC1(pIfObj) );
Vec_IntPush( vCopy, Gia_ManAppendAnd(pNew, iLit0, iLit1) );
}
