void InitEPwmGpio(void)
{
#if DSP28_EPWM1
InitEPwm1Gpio();
#endif // endif DSP28_EPWM1
#if DSP28_EPWM2
InitEPwm2Gpio();
#endif // endif DSP28_EPWM2
#if DSP28_EPWM3
InitEPwm3Gpio();
#endif // endif DSP28_EPWM3
#if DSP28_EPWM4
InitEPwm4Gpio();
#endif // endif DSP28_EPWM4
#if DSP28_EPWM5
InitEPwm5Gpio();
#endif // endif DSP28_EPWM5
#if DSP28_EPWM6
InitEPwm6Gpio();
#endif // endif DSP28_EPWM6
#if DSP28_EPWM7
InitEPwm7Gpio();
#endif // endif DSP28_EPWM7
#if DSP28_EPWM8
InitEPwm8Gpio();
#endif // endif DSP28_EPWM8
}
void InitEPwmGpio(void)
{
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
InitEPwm4Gpio();
InitEPwm5Gpio();
}
void InitEPwmGpio(void)
{
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
#if DSP28_EPWM4
InitEPwm4Gpio();
#endif // endif DSP28_EPWM4
}
//----------------------------------------------------------------------------------------------------------------------
void InitEPwm4(void){ // Function provided to initialize ePWM 4
InitEPwm4Gpio();
// Setup TBCLK
EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm4Regs.TBPRD = 1000; // Set timer period
EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm4Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm4Regs.TBCTR = 0x0000; // Clear counter
EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// Setup shadow register load on ZERO
EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Set Compare values
EPwm4Regs.CMPA.half.CMPA = 1000; // Set compare A value
EPwm4Regs.CMPB = 1000; // Set Compare B value
// Set Actions
EPwm4Regs.AQCTLA.bit.ZRO = AQ_NO_ACTION;
EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm4Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm4Regs.AQCTLA.bit.PRD = AQ_NO_ACTION;
EPwm4Regs.AQCTLB.bit.ZRO = AQ_NO_ACTION;
EPwm4Regs.AQCTLB.bit.PRD = AQ_NO_ACTION;
EPwm4Regs.AQCTLB.bit.CAU = AQ_CLEAR;
EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR;
// Active high complementary PWMs - Setup the deadband
/*EPwm4Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;
//EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HI;
//EPwm4Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm4Regs.DBCTL.bit.IN_MODE = DBB_RED_DBA_FED;
EPwm4Regs.DBRED = EPWM4_MIN_DB;
EPwm4Regs.DBFED = EPWM4_MIN_DB;
EPwm4_DB_Direction = DB_DOWN;*/
EPwm4Regs.DBCTL.bit.OUT_MODE = DBA_ENABLE;
EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HI;
EPwm4Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm4Regs.DBRED = EPWM4_MIN_DB;
EPwm4Regs.DBFED = EPWM4_MIN_DB;
// Interrupt where we will change the Compare Values
/*EPwm4Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm4Regs.ETSEL.bit.INTEN = 0; // Enable INT
EPwm4Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event*/
}
void InitEPwmGpio(void)
{
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
InitEPwm4Gpio();
#if DSP28_EPWM5
InitEPwm5Gpio();
#endif // endif DSP28_EPWM5
#if DSP28_EPWM6
InitEPwm6Gpio();
#endif // endif DSP28_EPWM6
}
void pwm_config(void)
{
pwm_output_disable();
Periodo_ticks = pwm_period_calculation(F_SAMP);
pwm1_config(); //pulsos disparo
pwm2_config(); //pulsos disparo
pwm3_config();
pwm4_config(); //DAC pwm
pwm5_config(); //Gera sinal CNVST para iniciar conversao do AD7634
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
InitEPwm4Gpio();
InitEPwm5Gpio();
pwm_mep_sfo_init();
}
void EPwmSetup()
{
// 使能前10个Epwm的I/O引脚
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
InitEPwm4Gpio();
InitEPwm5Gpio();
//InitEPwm6Gpio();
EPwm1Config(0, 0);
EPwm2Config(0, 0);
EPwm3Config(0, 0);
EPwm4Config(0, 0);
EPwm5Config(0, 0);
}
void main(void)
{
// WARNING: Always ensure you call memcpy before running any functions from RAM
// InitSysCtrl includes a call to a RAM based function and without a call to
// memcpy first, the processor will go "into the weeds"
#ifdef _FLASH
memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
#endif
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the f2802x_SysCtrl.c file.
InitSysCtrl();
// Step 2. Initialize GPIO:
// This example function is found in the f2802x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio(); // Skipped for this example
// For this case, just init GPIO for EPwm1-EPwm4
// For this case just init GPIO pins for EPwm1, EPwm2, EPwm3, EPwm4
// These functions are in the f2802x_EPwm.c file
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
InitEPwm4Gpio();
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the f2802x_PieCtrl.c file.
InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in f2802x_DefaultIsr.c.
// This function is found in f2802x_PieVect.c.
InitPieVectTable();
// Step 4. Initialize all the Device Peripherals:
// Not required for this example
// For this example, only initialize the EPwm
// Step 5. User specific code, enable interrupts:
update =1;
DutyFine =0;
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
// Some useful Period vs Frequency values
// SYSCLKOUT = 60 MHz 40 MHz
// --------------------------------------
// Period Frequency Frequency
// 1000 60 kHz 40 kHz
// 800 75 kHz 50 kHz
// 600 100 kHz 67 kHz
// 500 120 kHz 80 kHz
// 250 240 kHz 160 kHz
// 200 300 kHz 200 kHz
// 100 600 kHz 400 kHz
// 50 1.2 Mhz 800 kHz
// 25 2.4 Mhz 1.6 MHz
// 20 3.0 Mhz 2.0 MHz
// 12 5.0 MHz 3.3 MHz
// 10 6.0 MHz 4.0 MHz
// 9 6.7 MHz 4.4 MHz
// 8 7.5 MHz 5.0 MHz
// 7 8.6 MHz 5.7 MHz
// 6 10.0 MHz 6.6 MHz
// 5 12.0 MHz 8.0 MHz
//====================================================================
// ePWM and HRPWM register initialization
//====================================================================
HRPWM1_Config(10); // ePWM1 target, Period = 10
HRPWM2_Config(20); // ePWM2 target, Period = 20
HRPWM3_Config(10); // ePWM3 target, Period = 10
HRPWM4_Config(20); // ePWM4 target, Period = 20
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
while (update ==1)
{
for(DutyFine =1; DutyFine <256 ;DutyFine ++)
{
// Example, write to the HRPWM extension of CMPA
EPwm1Regs.CMPA.half.CMPAHR = DutyFine << 8; // Left shift by 8 to write into MSB bits
EPwm2Regs.CMPA.half.CMPAHR = DutyFine << 8; // Left shift by 8 to write into MSB bits
// Example, 32-bit write to CMPA:CMPAHR
EPwm3Regs.CMPA.all = ((Uint32)EPwm3Regs.CMPA.half.CMPA << 16) + (DutyFine << 8);
EPwm4Regs.CMPA.all = ((Uint32)EPwm4Regs.CMPA.half.CMPA << 16) + (DutyFine << 8);
for (i=0;i<10000;i++){} // Dummy delay between MEP changes
}
}
}
static void init_peripherals_drivers(void)
{
uint16_t i;
/// Initialization of HRADC boards
stop_DMA();
decimation_factor = (uint16_t) roundf(HRADC_FREQ_SAMP / ISR_CONTROL_FREQ);
decimation_coeff = 1.0 / (float) decimation_factor;
HRADCs_Info.enable_Sampling = 0;
HRADCs_Info.n_HRADC_boards = NUM_HRADC_BOARDS;
Init_DMA_McBSP_nBuffers(NUM_HRADC_BOARDS, decimation_factor, HRADC_SPI_CLK);
Init_SPIMaster_McBSP(HRADC_SPI_CLK);
Init_SPIMaster_Gpio();
InitMcbspa20bit();
DELAY_US(500000);
send_ipc_lowpriority_msg(0,Enable_HRADC_Boards);
DELAY_US(2000000);
for(i = 0; i < NUM_HRADC_BOARDS; i++)
{
Init_HRADC_Info(&HRADCs_Info.HRADC_boards[i], i, decimation_factor,
buffers_HRADC[i], TRANSDUCER_GAIN[i]);
Config_HRADC_board(&HRADCs_Info.HRADC_boards[i], TRANSDUCER_OUTPUT_TYPE[i],
HRADC_HEATER_ENABLE[i], HRADC_MONITOR_ENABLE[i]);
}
Config_HRADC_SoC(HRADC_FREQ_SAMP);
/**
*
* Initialization of PWM modules. PWM signals are mapped as the following:
*
* ePWM => Signal POF transmitter
* channel Name on BCB
*
* ePWM1A => Q1_MOD_1 PWM1
* ePWM1B => Q1_MOD_5 PWM2
* ePWM2A => Q2_MOD_1 PWM3
* ePWM2B => Q2_MOD_5 PWM4
* ePWM3A => Q1_MOD_2 PWM5
* ePWM3B => Q1_MOD_6 PWM6
* ePWM4A => Q2_MOD_2 PWM7
* ePWM4B => Q2_MOD_6 PWM8
* ePWM5A => Q1_MOD_3 PWM9
* ePWM5B => Q1_MOD_7 PWM10
* ePWM6A => Q2_MOD_3 PWM11
* ePWM6B => Q2_MOD_7 PWM12
* ePWM7A => Q1_MOD_4 PWM13
* ePWM7B => Q1_MOD_8 PWM14
* ePWM8A => Q2_MOD_4 PWM15
* ePWM8B => Q2_MOD_8 PWM16
*
*/
g_pwm_modules.num_modules = 8;
PWM_MODULATOR_Q1_MOD_1_5 = &EPwm1Regs;
PWM_MODULATOR_Q2_MOD_1_5 = &EPwm2Regs;
PWM_MODULATOR_Q1_MOD_2_6 = &EPwm3Regs;
PWM_MODULATOR_Q2_MOD_2_6 = &EPwm4Regs;
PWM_MODULATOR_Q1_MOD_3_7 = &EPwm5Regs;
PWM_MODULATOR_Q2_MOD_3_7 = &EPwm6Regs;
PWM_MODULATOR_Q1_MOD_4_8 = &EPwm7Regs;
PWM_MODULATOR_Q2_MOD_4_8 = &EPwm8Regs;
disable_pwm_outputs();
disable_pwm_tbclk();
init_pwm_mep_sfo();
init_pwm_module(PWM_MODULATOR_Q1_MOD_1_5, PWM_FREQ, 0, PWM_Sync_Master, 0,
PWM_ChB_Independent, PWM_DEAD_TIME);
init_pwm_module(PWM_MODULATOR_Q2_MOD_1_5, PWM_FREQ, 1, PWM_Sync_Slave, 180,
PWM_ChB_Independent, PWM_DEAD_TIME);
cfg_pwm_module_h_brigde_q2(PWM_MODULATOR_Q2_MOD_1_5);
init_pwm_module(PWM_MODULATOR_Q1_MOD_2_6, PWM_FREQ, 0, PWM_Sync_Slave, 45,
PWM_ChB_Independent, PWM_DEAD_TIME);
init_pwm_module(PWM_MODULATOR_Q2_MOD_2_6, PWM_FREQ, 3, PWM_Sync_Slave, 225,
PWM_ChB_Independent, PWM_DEAD_TIME);
cfg_pwm_module_h_brigde_q2(PWM_MODULATOR_Q2_MOD_2_6);
init_pwm_module(PWM_MODULATOR_Q1_MOD_3_7, PWM_FREQ, 0, PWM_Sync_Slave, 90,
PWM_ChB_Independent, PWM_DEAD_TIME);
init_pwm_module(PWM_MODULATOR_Q2_MOD_3_7, PWM_FREQ, 5, PWM_Sync_Slave, 270,
PWM_ChB_Independent, PWM_DEAD_TIME);
cfg_pwm_module_h_brigde_q2(PWM_MODULATOR_Q2_MOD_3_7);
init_pwm_module(PWM_MODULATOR_Q1_MOD_4_8, PWM_FREQ, 0, PWM_Sync_Slave, 135,
PWM_ChB_Independent, PWM_DEAD_TIME);
init_pwm_module(PWM_MODULATOR_Q2_MOD_4_8, PWM_FREQ, 7, PWM_Sync_Slave, 315,
PWM_ChB_Independent, PWM_DEAD_TIME);
cfg_pwm_module_h_brigde_q2(PWM_MODULATOR_Q2_MOD_4_8);
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
InitEPwm4Gpio();
InitEPwm5Gpio();
InitEPwm6Gpio();
InitEPwm7Gpio();
InitEPwm8Gpio();
/// Initialization of timers
InitCpuTimers();
ConfigCpuTimer(&CpuTimer0, C28_FREQ_MHZ, 1000000);
CpuTimer0Regs.TCR.bit.TIE = 0;
}
