/**
* \brief Initialize the AINTC by enabling normal interrupts (IRQ) and fast interrupts (FIQ) on all required levels
*
* \return none
**/
void interrupt_init(void) {
/* Initialize AINTC - this should only be done once per application */
IntAINTCInit();
/* Enable IRQ for ARM (in CPSR)*/
IntMasterIRQEnable();
/* Enable AINTC interrupts in GER */
IntGlobalEnable();
/* Enable IRQ in AINTC */
IntIRQEnable();
IntMasterFIQEnable();
IntFIQEnable();
}
void configEMIFOPP100(void)
{
/* Disable interrupts */
IntMasterIRQDisable();
IntMasterFIQDisable();
/* DDR2 in SR */
HWREG(SOC_EMIF_0_REGS + EMIF_PWR_MGMT_CTRL) |=
((EMIF_PWR_MGMT_CTRL_REG_LP_MODE_SELFREFRESH <<
EMIF_PWR_MGMT_CTRL_REG_LP_MODE_SHIFT) & EMIF_PWR_MGMT_CTRL_REG_LP_MODE);
/* Give a delay */
//for(loopIdx = 0;(loopIdx < PM_DELAY_COUNT);loopIdx++) {}
/* PLL Configuration */
/* MN bypass */
HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_CLKMODE_DPLL_DDR) =
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_CLKMODE_DPLL_DDR) &
(~CM_WKUP_CM_CLKMODE_DPLL_DDR_DPLL_EN)) |
CM_WKUP_CM_CLKMODE_DPLL_DDR_DPLL_EN_DPLL_MN_BYP_MODE;
while(((HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_IDLEST_DPLL_DDR)) &
CM_WKUP_CM_IDLEST_DPLL_DDR_ST_MN_BYPASS )!=
CM_WKUP_CM_IDLEST_DPLL_DDR_ST_MN_BYPASS);
/* M & N */
HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_CLKSEL_DPLL_DDR) =
(PM_OPP100_DDR_M << CM_WKUP_CM_CLKSEL_DPLL_DDR_DPLL_MULT_SHIFT) |
(PM_OPP100_DDR_N);
/* M2 */
HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_DIV_M2_DPLL_DDR) =
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_DIV_M2_DPLL_DDR) &
(~CM_WKUP_CM_DIV_M2_DPLL_DDR_DPLL_CLKOUT_DIV)) | (PM_OPP100_DDR_M2);
/* PLL Relock */
HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_CLKMODE_DPLL_DDR) =
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_CLKMODE_DPLL_DDR) &
(~CM_WKUP_CM_CLKMODE_DPLL_DDR_DPLL_EN)) |
CM_WKUP_CM_CLKMODE_DPLL_DDR_DPLL_EN_DPLL_LOCK_MODE;
while(((HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_IDLEST_DPLL_DDR)) &
CM_WKUP_CM_IDLEST_DPLL_DDR_ST_DPLL_CLK )!=
CM_WKUP_CM_IDLEST_DPLL_DDR_ST_DPLL_CLK_DPLL_LOCKED);
/* EMIF PRCM */
/* Enable EMIF4DC Firewall clocks*/
HWREG(SOC_CM_PER_REGS + CM_PER_EMIF_FW_CLKCTRL) =
(HWREG(SOC_CM_PER_REGS + CM_PER_EMIF_FW_CLKCTRL) &
CM_PER_EMIF_FW_CLKCTRL_MODULEMODE) | CM_PER_EMIF_FW_CLKCTRL_MODULEMODE_ENABLE;
/* Enable EMIF4DC clocks*/
HWREG(SOC_CM_PER_REGS + CM_PER_EMIF_CLKCTRL) =
(HWREG(SOC_CM_PER_REGS + CM_PER_EMIF_CLKCTRL) & (~CM_PER_EMIF_CLKCTRL_MODULEMODE)) |
CM_PER_EMIF_CLKCTRL_MODULEMODE_ENABLE;
/* Poll for module is functional */
while(HWREG(SOC_CM_PER_REGS + CM_PER_EMIF_CLKCTRL) !=
CM_PER_EMIF_CLKCTRL_MODULEMODE_ENABLE);
/*CMD REG PHY*/
HWREG(CMD0_REG_PHY_CTRL_SLAVE_RATIO_0) = DDR2_REG_PHY_CTRL_SLAVE_RATIO;
HWREG(CMD0_REG_PHY_CTRL_SLAVE_FORCE_0) = 0;
HWREG(CMD0_REG_PHY_CTRL_SLAVE_DELAY_0) = 0;
HWREG(CMD0_REG_PHY_DLL_LOCK_DIFF_0) = 0;
HWREG(CMD0_REG_PHY_INVERT_CLKOUT_0) = 0;
HWREG(CMD1_REG_PHY_CTRL_SLAVE_RATIO_0) = DDR2_REG_PHY_CTRL_SLAVE_RATIO;
HWREG(CMD1_REG_PHY_CTRL_SLAVE_FORCE_0) = 0;
HWREG(CMD1_REG_PHY_CTRL_SLAVE_DELAY_0) = 0;
HWREG(CMD1_REG_PHY_DLL_LOCK_DIFF_0) = 0;
HWREG(CMD1_REG_PHY_INVERT_CLKOUT_0) = 0;
HWREG(CMD2_REG_PHY_CTRL_SLAVE_RATIO_0) = DDR2_REG_PHY_CTRL_SLAVE_RATIO;
HWREG(CMD2_REG_PHY_CTRL_SLAVE_FORCE_0) = 0;
HWREG(CMD2_REG_PHY_CTRL_SLAVE_DELAY_0) = 0;
HWREG(CMD2_REG_PHY_DLL_LOCK_DIFF_0) = 0;
HWREG(CMD2_REG_PHY_INVERT_CLKOUT_0) = 0;
/*DATA0 and DATA1 PHY config*/
HWREG(DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0) = (((DDR2_PHY_RD_DQS_SLAVE_RATIO<<30)|(DDR2_PHY_RD_DQS_SLAVE_RATIO<<20)|
(DDR2_PHY_RD_DQS_SLAVE_RATIO <<10)|(DDR2_PHY_RD_DQS_SLAVE_RATIO<<0)));
HWREG(DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_1) = DDR2_PHY_RD_DQS_SLAVE_RATIO>>2;
HWREG(DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0) = 0;
HWREG(DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_1) = 0;
HWREG(DATA0_REG_PHY_WRLVL_INIT_RATIO_0) = 0;
HWREG(DATA0_REG_PHY_WRLVL_INIT_RATIO_1) = 0;
HWREG(DATA0_REG_PHY_GATELVL_INIT_RATIO_0) = 0;
HWREG(DATA0_REG_PHY_GATELVL_INIT_RATIO_1) = 0;
HWREG(DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0)= (((DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO<<30)|(DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO<<20)|
(DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO<<10)|(DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO<<0)));
HWREG(DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_1)= DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO>>2;
HWREG(DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0)= (((DDR2_REG_PHY_WR_DATA_SLAVE_RATIO<<30)|(DDR2_REG_PHY_WR_DATA_SLAVE_RATIO<<20)|
(DDR2_REG_PHY_WR_DATA_SLAVE_RATIO<<10)|(DDR2_REG_PHY_WR_DATA_SLAVE_RATIO<<0)));
HWREG(DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_1)= DDR2_REG_PHY_WR_DATA_SLAVE_RATIO>>2;
HWREG(DATA0_REG_PHY_DLL_LOCK_DIFF_0) = 0;
HWREG(DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0) = (((DDR2_PHY_RD_DQS_SLAVE_RATIO<<30)|(DDR2_PHY_RD_DQS_SLAVE_RATIO<<20)|
(DDR2_PHY_RD_DQS_SLAVE_RATIO <<10)|(DDR2_PHY_RD_DQS_SLAVE_RATIO<<0)));
HWREG(DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_1) = DDR2_PHY_RD_DQS_SLAVE_RATIO>>2;
HWREG(DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0) = 0;
HWREG(DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_1) = 0;
HWREG(DATA1_REG_PHY_WRLVL_INIT_RATIO_0) = 0;
HWREG(DATA1_REG_PHY_WRLVL_INIT_RATIO_1) = 0;
HWREG(DATA1_REG_PHY_GATELVL_INIT_RATIO_0) = 0;
HWREG(DATA1_REG_PHY_GATELVL_INIT_RATIO_1) = 0;
HWREG(DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_0)= (((DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO<<30)|(DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO<<20)|
(DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO<<10)|(DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO<<0)));
HWREG(DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_1)= DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO>>2;
HWREG(DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_0)= (((DDR2_REG_PHY_WR_DATA_SLAVE_RATIO<<30)|(DDR2_REG_PHY_WR_DATA_SLAVE_RATIO<<20)|
(DDR2_REG_PHY_WR_DATA_SLAVE_RATIO<<10)|(DDR2_REG_PHY_WR_DATA_SLAVE_RATIO<<0)));
HWREG(DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_1)= DDR2_REG_PHY_WR_DATA_SLAVE_RATIO>>2;
HWREG(DATA1_REG_PHY_DLL_LOCK_DIFF_0) = 0;
/* IO configuration*/
//IO to work for mDDR
//HWREG(SOC_CONTROL_REGS + CONTROL_DDR_IO_CTRL) |= 0x10000000;
HWREG(SOC_CONTROL_REGS + CONTROL_DDR_CMD_IOCTRL(0)) |= PM_DDR_IO_CONTROL;
HWREG(SOC_CONTROL_REGS + CONTROL_DDR_CMD_IOCTRL(1)) |= PM_DDR_IO_CONTROL;
HWREG(SOC_CONTROL_REGS + CONTROL_DDR_CMD_IOCTRL(2)) |= PM_DDR_IO_CONTROL;
HWREG(SOC_CONTROL_REGS + CONTROL_DDR_DATA_IOCTRL(0)) |= PM_DDR_IO_CONTROL;
HWREG(SOC_CONTROL_REGS + CONTROL_DDR_DATA_IOCTRL(1)) |= PM_DDR_IO_CONTROL;
//CKE controlled by EMIF/DDR_PHY
HWREG(SOC_CONTROL_REGS + CONTROL_DDR_CKE_CTRL) |= 0x00000001;
/*EMIF Timings*/
HWREG(SOC_EMIF_0_REGS + EMIF_DDR_PHY_CTRL_1) = OPP100_DDR2_READ_LATENCY;
HWREG(SOC_EMIF_0_REGS + EMIF_DDR_PHY_CTRL_1_SHDW) = OPP100_DDR2_READ_LATENCY;
HWREG(SOC_EMIF_0_REGS + EMIF_DDR_PHY_CTRL_2) = OPP100_DDR2_READ_LATENCY;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_TIM_1) = OPP100_DDR2_SDRAM_TIMING1;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_TIM_1_SHDW) = OPP100_DDR2_SDRAM_TIMING1;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_TIM_2) = OPP100_DDR2_SDRAM_TIMING2;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_TIM_2_SHDW) = OPP100_DDR2_SDRAM_TIMING2;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_TIM_3) = OPP100_DDR2_SDRAM_TIMING3;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_TIM_3_SHDW) = OPP100_DDR2_SDRAM_TIMING3;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_REF_CTRL) = OPP100_DDR2_REF_CTRL;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_REF_CTRL_SHDW) = OPP100_DDR2_REF_CTRL;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_CONFIG) = OPP100_DDR2_SDRAM_CONFIG;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_CONFIG_2) = OPP100_DDR2_SDRAM_CONFIG;
/* DDR out of SR */
HWREG(SOC_EMIF_0_REGS + EMIF_PWR_MGMT_CTRL) &=
~((EMIF_PWR_MGMT_CTRL_REG_LP_MODE_SELFREFRESH <<
EMIF_PWR_MGMT_CTRL_REG_LP_MODE_SHIFT) & EMIF_PWR_MGMT_CTRL_REG_LP_MODE);
/* Enable interrupts */
IntMasterFIQEnable();
IntMasterIRQEnable();
}