void initTimer1(void)
{
sensorTurn=0;
SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER1);
IntMasterEnable();
TimerConfigure(TIMER1_BASE, TIMER_CFG_PERIODIC);
TimerLoadSet(TIMER1_BASE, TIMER_A, g_SysClock);
IntPriorityGroupingSet(4);
IntPrioritySet(INT_TIMER0A, 0xF0);
IntEnable(INT_TIMER1A);
TimerIntEnable(TIMER1_BASE, TIMER_TIMA_TIMEOUT);
}
void initTimer()
{
SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER0);
IntMasterEnable();
TimerConfigure(TIMER0_BASE, TIMER_CFG_PERIODIC);
TimerLoadSet(TIMER0_BASE, TIMER_A, g_SysClock/5);
IntPriorityGroupingSet(4);
IntPrioritySet(INT_TIMER0A, 0xE0);
IntEnable(INT_TIMER0A);
TimerIntEnable(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
TimerEnable(TIMER0_BASE, TIMER_A);
timer0_status=1;
}
void prvSetupHardware( void ){
tBoolean found;
long lEEPROMRetStatus;
unsigned short data,data2;
unsigned long uart_speed;
/* If running on Rev A2 silicon, turn the LDO voltage up to 2.75V. This is
a workaround to allow the PLL to operate reliably. */
if( DEVICE_IS_REVA2 ) {
SysCtlLDOSet( SYSCTL_LDO_2_75V );
}
/* Set the clocking to run from the PLL at 50 MHz */
SysCtlClockSet( SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ );
/* Enable Port F for Ethernet LEDs
LED0 Bit 3 Output
LED1 Bit 2 Output */
SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOF );
GPIODirModeSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3), GPIO_DIR_MODE_HW );
GPIOPadConfigSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3 ), GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD );
//
// Enable the GPIO pin for the LED (PF0). Set the direction as output, and
// enable the GPIO pin for digital function.
//
GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_0);
//
// Enable processor interrupts.
//
IntMasterEnable();
if(SoftEEPROMInit(0x1F000, 0x20000, 0x800) != 0) {
LWIPDebug("SoftEEPROM initialisation failed.");
}
lEEPROMRetStatus = SoftEEPROMRead(UART0_SPEED_HIGH_ID, &data, &found);
if(lEEPROMRetStatus == 0 && found) {
SoftEEPROMRead(UART0_SPEED_LOW_ID, &data2, &found);
uart_speed = (data << 16 & 0xFFFF0000) | (data2 & 0x0000FFFF);
SoftEEPROMRead(UART0_CONFIG_ID, &data, &found);
} else {
uart_speed=115200;
data = (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE);
}
uart_init(0, uart_speed, data);
SysCtlPeripheralEnable(SYSCTL_PERIPH_WDOG0);
IntPriorityGroupingSet(4);
IntPrioritySet(INT_WATCHDOG,SET_SYSCALL_INTERRUPT_PRIORITY(5));
IntEnable(INT_WATCHDOG); // Enable the watchdog interrupt.
WatchdogReloadSet(WATCHDOG0_BASE, SysCtlClockGet());
WatchdogResetEnable(WATCHDOG0_BASE);
WatchdogEnable(WATCHDOG0_BASE);
rtc_init();
modules_init();
}
error_t tm4c129EthInit(NetInterface *interface)
{
//Debug message
TRACE_INFO("Initializing Tiva TM4C129 Ethernet controller...\r\n");
//Save underlying network interface
nicDriverInterface = interface;
//Enable Ethernet controller clock
SysCtlPeripheralEnable(SYSCTL_PERIPH_EMAC0);
//Reset Ethernet controller
SysCtlPeripheralReset(SYSCTL_PERIPH_EMAC0);
//Wait for the reset to complete
while(!SysCtlPeripheralReady(SYSCTL_PERIPH_EMAC0));
//Enable internal PHY clock
SysCtlPeripheralEnable(SYSCTL_PERIPH_EPHY0);
//Reset internal PHY
SysCtlPeripheralReset(SYSCTL_PERIPH_EPHY0);
//Wait for the reset to complete
while(!SysCtlPeripheralReady(SYSCTL_PERIPH_EPHY0));
//GPIO configuration
tm4c129EthInitGpio(interface);
//Perform a software reset
EMAC0_DMABUSMOD_R |= EMAC_DMABUSMOD_SWR;
//Wait for the reset to complete
while(EMAC0_DMABUSMOD_R & EMAC_DMABUSMOD_SWR);
//Adjust MDC clock range depending on SYSCLK frequency
EMAC0_MIIADDR_R = EMAC_MIIADDR_CR_100_150;
//Reset PHY transceiver
tm4c129EthWritePhyReg(EPHY_BMCR, EPHY_BMCR_MIIRESET);
//Wait for the reset to complete
while(tm4c129EthReadPhyReg(EPHY_BMCR) & EPHY_BMCR_MIIRESET);
//Dump PHY registers for debugging purpose
tm4c129EthDumpPhyReg();
//Configure LED0, LED1 and LED2
tm4c129EthWritePhyReg(EPHY_LEDCFG, EPHY_LEDCFG_LED0_TX |
EPHY_LEDCFG_LED1_RX | EPHY_LEDCFG_LED2_LINK);
//Configure PHY interrupts as desired
tm4c129EthWritePhyReg(EPHY_MISR1, EPHY_MISR1_LINKSTATEN);
//Enable PHY interrupts
tm4c129EthWritePhyReg(EPHY_SCR, EPHY_SCR_INTEN);
//Use default MAC configuration
EMAC0_CFG_R = EMAC_CFG_DRO;
//Set the MAC address
EMAC0_ADDR0L_R = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
EMAC0_ADDR0H_R = interface->macAddr.w[2];
//Initialize hash table
EMAC0_HASHTBLL_R = 0;
EMAC0_HASHTBLH_R = 0;
//Configure the receive filter
EMAC0_FRAMEFLTR_R = EMAC_FRAMEFLTR_HPF | EMAC_FRAMEFLTR_HMC;
//Disable flow control
EMAC0_FLOWCTL_R = 0;
//Enable store and forward mode
EMAC0_DMAOPMODE_R = EMAC_DMAOPMODE_RSF | EMAC_DMAOPMODE_TSF;
//Configure DMA bus mode
EMAC0_DMABUSMOD_R = EMAC_DMABUSMOD_AAL | EMAC_DMABUSMOD_USP | EMAC_DMABUSMOD_RPBL_1 |
EMAC_DMABUSMOD_PR_1_1 | EMAC_DMABUSMOD_PBL_1 | EMAC_DMABUSMOD_ATDS;
//Initialize DMA descriptor lists
tm4c129EthInitDmaDesc(interface);
//Prevent interrupts from being generated when the transmit statistic
//counters reach half their maximum value
EMAC0_MMCTXIM_R = EMAC_MMCTXIM_OCTCNT | EMAC_MMCTXIM_MCOLLGF |
EMAC_MMCTXIM_SCOLLGF | EMAC_MMCTXIM_GBF;
//Prevent interrupts from being generated when the receive statistic
//counters reach half their maximum value
EMAC0_MMCRXIM_R = EMAC_MMCRXIM_UCGF | EMAC_MMCRXIM_ALGNERR |
EMAC_MMCRXIM_CRCERR | EMAC_MMCRXIM_GBF;
//Disable MAC interrupts
EMAC0_IM_R = EMAC_IM_TSI | EMAC_IM_PMT;
//Enable the desired DMA interrupts
EMAC0_DMAIM_R = EMAC_DMAIM_NIE | EMAC_DMAIM_RIE | EMAC_DMAIM_TIE;
//Enable PHY interrupts
EMAC0_EPHYIM_R = EMAC_EPHYIM_INT;
//Set priority grouping (3 bits for pre-emption priority, no bits for subpriority)
IntPriorityGroupingSet(TM4C129_ETH_IRQ_PRIORITY_GROUPING);
//Configure Ethernet interrupt priority
IntPrioritySet(INT_EMAC0, TM4C129_ETH_IRQ_PRIORITY);
//Enable MAC transmission and reception
EMAC0_CFG_R |= EMAC_CFG_TE | EMAC_CFG_RE;
//Enable DMA transmission and reception
EMAC0_DMAOPMODE_R |= EMAC_DMAOPMODE_ST | EMAC_DMAOPMODE_SR;
//Accept any packets from the upper layer
osSetEvent(&interface->nicTxEvent);
//Successful initialization
return NO_ERROR;
}
