BOOL DelaySlotAffectBranch(DWORD PC) {
OPCODE Branch, Delay;
OPCODE_INFO infoBranch, infoDelay;
if (IsOpcodeNop(PC + 4) == TRUE) {
return FALSE;
}
RSP_LW_IMEM(PC, &Branch.Hex);
RSP_LW_IMEM(PC+4, &Delay.Hex);
memset(&infoDelay,0,sizeof(infoDelay));
memset(&infoBranch,0,sizeof(infoBranch));
GetInstructionInfo(PC, &Branch, &infoBranch);
GetInstructionInfo(PC+4, &Delay, &infoDelay);
if ((infoDelay.flags & COPO_MF_Instruction) == COPO_MF_Instruction) {
return TRUE;
}
if ((infoDelay.flags & Instruction_Mask) == VEC_Instruction) {
return FALSE;
}
if (infoBranch.SourceReg0 == infoDelay.DestReg) { return TRUE; }
if (infoBranch.SourceReg1 == infoDelay.DestReg) { return TRUE; }
return FALSE;
}
int32_t DelaySlotAffectBranch(uint32_t PC)
{
RSPOPCODE Branch, Delay;
OPCODE_INFO infoBranch, infoDelay;
if (IsOpcodeNop(PC + 4) == 1) {
return 0;
}
RSP_LW_IMEM(PC, &Branch.Hex);
RSP_LW_IMEM(PC + 4, &Delay.Hex);
memset(&infoDelay, 0, sizeof(infoDelay));
memset(&infoBranch, 0, sizeof(infoBranch));
GetInstructionInfo(PC, &Branch, &infoBranch);
GetInstructionInfo(PC + 4, &Delay, &infoDelay);
if ((infoDelay.flags & Instruction_Mask) == VEC_Instruction) {
return 0;
}
if (infoBranch.SourceReg0 == infoDelay.DestReg) {
return 1;
}
if (infoBranch.SourceReg1 == infoDelay.DestReg) {
return 1;
}
return 0;
}