bool TransactionConflictManager::isRemoteOlder(int thread, int remote_thread, uint64 local_timestamp, uint64 remote_timestamp, MachineID remote_id){ assert(local_timestamp != 0); assert(remote_timestamp != 0); /* if(remote_timestamp == 0){ int remote_processor = L1CacheMachIDToProcessorNum(remote_id); int remote_chip = remote_processor / RubyConfig::numberOfProcsPerChip(); int remote_chip_ver = remote_processor % RubyConfig::numberOfProcsPerChip(); cout << " " << g_eventQueue_ptr->getTime() << " " << getLogicalProcID(thread) << " [" << getProcID() << "," << thread << "] REMOTE_TIMESTAMP is 0 remote_id: " << remote_processor << endl; TransactionInterfaceManager* remote_mgr = g_system_ptr->getChip(remote_chip)->getTransactionInterfaceManager(remote_chip_ver); for (int i = 0; i < RubyConfig::numberofSMTThreads(); i++) cout << "[ " << i << " XACT_LEVEL: " << remote_mgr->getTransactionLevel(i) << " TIMESTAMP: " << remote_mgr->getXactConflictManager()->getTimestamp(i) << "] "; cout << " current time: " << g_eventQueue_ptr->getTime() << endl; assert(0); } */ bool older = false; if (local_timestamp == remote_timestamp){ if (getProcID() == (int) L1CacheMachIDToProcessorNum(remote_id)){ older = (remote_thread < thread); } else { older = (int) L1CacheMachIDToProcessorNum(remote_id) < getProcID(); } } else { older = (remote_timestamp < local_timestamp); } return older; }
void TransactionConflictManager::notifyReceiveNack(int thread, Address physicalAddr, uint64 local_timestamp, uint64 remote_timestamp, MachineID remote_id){ bool possible_cycle = m_possible_cycle[thread]; // get the remote thread that NACKed us int remote_procnum = L1CacheMachIDToProcessorNum(remote_id); TransactionConflictManager * remote_conflict_mgr = g_system_ptr->getChip(m_chip_ptr->getID())->getTransactionInterfaceManager(remote_procnum)->getXactConflictManager(); int remote_thread = remote_conflict_mgr->getOldestThread(); int remote_logicalprocnum = remote_procnum*RubyConfig::numberofSMTThreads()+remote_thread; int my_logicalprocnum = getLogicalProcID(thread); Address myPC = SIMICS_get_program_counter(my_logicalprocnum); Address remotePC = SIMICS_get_program_counter(remote_logicalprocnum); //const char * my_instruction = SIMICS_disassemble_physical( my_logicalprocnum, SIMICS_translate_address( my_logicalprocnum, myPC )); //const char * remote_instruction = SIMICS_disassemble_physical( remote_logicalprocnum, SIMICS_translate_address( remote_logicalprocnum, remotePC )); m_nackedBy[thread][remote_logicalprocnum] = true; m_nackedByTimestamp[thread][remote_logicalprocnum] = remote_timestamp; m_magicWaitingTime[thread] = remote_timestamp; m_magicWaitingOn[thread] = remote_logicalprocnum; if (possible_cycle && isRemoteOlder(thread, remote_thread, local_timestamp, remote_timestamp, remote_id)){ m_shouldTrap[thread] = true; } if (XACT_DEBUG && (XACT_DEBUG_LEVEL > 2)){ cout << " " << g_eventQueue_ptr->getTime() << " " << getLogicalProcID(thread) << " [" << getProcID() << "," << thread << "] RECEIVED NACK " << physicalAddr << " remote_id: " << remote_logicalprocnum << " [" << remote_procnum << "," << remote_thread << "] myPC: " << myPC << " remotePC: " << remotePC << " local_timestamp: " << local_timestamp << " remote_timestamp: " << remote_timestamp << " shouldTrap " << m_shouldTrap[thread] << endl; } }
void profileOverflow(const Address & addr, MachineID mach) { if(mach.type == MACHINETYPE_L1CACHE_ENUM){ // for L1 overflows int proc_num = L1CacheMachIDToProcessorNum(mach); int chip_num = proc_num/RubyConfig::numberOfProcsPerChip(); g_system_ptr->getChip(chip_num)->m_L1Cache_xact_mgr_vec[proc_num]->profileOverflow(addr, true); } else if(mach.type == MACHINETYPE_L2CACHE_ENUM){ // for L2 overflows int chip_num = L2CacheMachIDToChipID(mach); for(int p=0; p < RubyConfig::numberOfProcessors(); ++p){ g_system_ptr->getChip(chip_num)->m_L1Cache_xact_mgr_vec[p]->profileOverflow(addr, false); } } }
void TransactionConflictManager::notifySendNack(Address physicalAddress, uint64 remote_timestamp, MachineID remote_id){ // get the remote thread that NACKed us int remote_procnum = L1CacheMachIDToProcessorNum(remote_id); TransactionConflictManager * remote_conflict_mgr = g_system_ptr->getChip(m_chip_ptr->getID())->getTransactionInterfaceManager(remote_procnum)->getXactConflictManager(); int remote_thread = remote_conflict_mgr->getOldestThread(); //assert(RubyConfig::numberofSMTThreads() == 1); for (int i = 0; i < RubyConfig::numberofSMTThreads(); i++){ if (XACT_MGR->isInReadSetFilter(i, physicalAddress) || XACT_MGR->isInWriteSetFilter(i, physicalAddress)){ bool writer = XACT_MGR->isInWriteSetFilter(i, physicalAddress) ? true:false; if (isRemoteOlder(i, remote_thread, m_timestamp[i], remote_timestamp, remote_id)){ // if (XACT_DEBUG && (XACT_DEBUG_LEVEL > 1)){ // cout << " " << g_eventQueue_ptr->getTime() << " " << getLogicalProcID(i) << " [" << getProcID() << "," << i << "] SETTING POSSIBLE CYCLE FLAG " << physicalAddress << " remote_id: " << L1CacheMachIDToProcessorNum(remote_id) << endl; // } setPossibleCycle(i); //m_magicWaitingTime[i] = remote_timestamp; //m_magicWaitingOn[i] = L1CacheMachIDToProcessorNum(remote_id) * RubyConfig::numberofSMTThreads() + remote_thread; } } } }
// Public Methods void Dram::wakeup() { //cerr << "wakeup DRAM: " << m_version << " " << g_eventQueue_ptr->getTime() << endl; if(DEBUG_DRAM && !g_CARGA_CACHE ) cerr << "wakeup DRAM: " << g_eventQueue_ptr->getTime() <<" version:" << m_version<< " nm:" << RubyConfig::numberOfMemories() << endl; dramRequest req; req.valid=false; //nos llega una peticion por ciclo (de cpu) a cada controlador de memoria if(m_version<RubyConfig::numberOfMemories()) { prefMSHRsize.add(prefMSHR.size()); req= Dram::getRequestFromMSHR(m_version); if(DEBUG_DRAM && !g_CARGA_CACHE && req.valid) { cerr << "wakeup (m_version):" << m_version << endl; cerr << "wakeup (addr):" << req.addr << endl; cerr << "wakeup (requestor):" << req.requestor<< endl; cerr << "wakeup (valid):" << req.valid<< endl; } if(DEBUG_WRITE && !g_CARGA_CACHE && req.valid && req.write) { cerr << "wakeup (m_version):" << m_version << endl; cerr << "wakeup (addr):" << req.addr << endl; cerr << "wakeup (requestor):" << req.requestor<< endl; cerr << "wakeup (valid):" << req.valid<< endl; cerr << "wakeup (MSHRtime):" << req.MSHRTime<< endl; cerr << "wakeup (Time in MSHR):" << g_eventQueue_ptr->getTime() - req.MSHRTime<< endl; cerr << "wakeup [now]:" << g_eventQueue_ptr->getTime()<< endl; } if(req.valid) request(req); int i,j; dramRequest request; bool hit; if(!g_CARGA_CACHE && !(g_eventQueue_ptr->getTime()%freqRatio)) { //taux=0; if(DEBUG_DRAM && !g_CARGA_CACHE ) cerr << "wakeup DRAM "<< m_version << " acciones: " << g_eventQueue_ptr->getTime() << endl; if(DEBUG_DRAM && !g_CARGA_CACHE ) { cout << "bankBusyBitmap: " ; for(i=0; i< numOfBanks; i++) cout << banks[i].bankBusyBitmap ; cout << endl << "Tama–o demandQueue=" ; for(i=0; i< numOfBanks; i++) cout <<banks[i].demandQueue.size() << " "; cout << endl << "Tama–o prefetchQueue=" ; for(i=0; i< numOfBanks; i++) cout << banks[i].prefetchQueue.size() << " "; cout << endl << "Pagina abierta: " ; for(i=0; i< numOfBanks; i++) cout << banks[i].pageTAG << " " ; cout << endl <<endl << "busBusyBitmap: " << busBusyBitmap << endl; cout << "primera petici—n en el bus: " << bus.top().addr << " de la L2 " << bus.top().requestor << endl; } //Para cada banco insertamos petici—n si toca int aux=0; for(i=0; i< numOfBanks; i++) { banks[i].bankBusyBitmap & 1 ? aux++ : 0; banks[i].bankBusyBitmap >>= 1; } busyBanks.add(aux); //stats cyclesDRAM++; busBusyBitmap & 1 ? cyclesBusBusy++ : 0; busBusyBitmap >>= 1; //cout << "despues: \t" << binary(busBusyBitmap) << "\t" << busBusyBitmap << "\t" <<g_eventQueue_ptr->getTime() <<endl; //tenemos que sacar algo del bus? if(bus.size() > 0 && bus.top().wakeUp <= g_eventQueue_ptr->getTime()) { request=bus.top(); // if(request.wakeUp < taux) cout << "temporizaci—n err—nea" << endl, exit(-1); //taux=request.wakeUp; bus.pop(); if(DEBUG_DRAM && !g_CARGA_CACHE) cout << "petici—n lista: " << request.addr << endl; if(DEBUG_WRITE && !g_CARGA_CACHE && request.write) cout << "Ready write: " << request.addr << endl; if(DEBUG_WRITE && !g_CARGA_CACHE && request.write) cout << "a:" << g_eventQueue_ptr->getTime() - request.queueTime << " " << g_eventQueue_ptr->getTime() << " " << request.wakeUp << endl; //read request has to send the data to the LLC if(!request.write) { //podemos mandar el dato a la L2! ResponseMsg out_msg; (out_msg).m_Address = request.addr; //CAMBIAR PARA A„ADIR ESCRITURA!!! (out_msg).m_Type = CoherenceResponseType_DATA; (out_msg).m_MessageSize = MessageSizeType_Data; (out_msg).m_RequestorMachId = request.requestor; (((out_msg).m_Destination).add((map_Address_to_L2(request.addr)))); // if(!g_CARGA_CACHE) cout << "a:" << g_eventQueue_ptr->getTime() - request.queueTime << " " << g_eventQueue_ptr->getTime() << " " << request.wakeUp << endl; if(DEBUG_DRAM && !g_CARGA_CACHE) cout << "petici—n lista: " << request.addr << endl; DEBUG_SLICC(MedPrio, "DramWakeup (sent message): ", out_msg); DEBUG_SLICC(MedPrio, "DramWakeup (L2 destination): ", map_Address_to_L2Node(request.addr)); //m_chip_ptr->m_Directory_dramToDirQueue_vec[0]->enqueue(out_msg, 1); if(request.demand)m_chip_ptr->m_L2Cache_responseToL2CacheQueue_vec[map_Address_to_L2Node(request.addr)]->enqueue(out_msg, 1); else m_chip_ptr->m_L2Cache_prefResponseToL2CacheQueue_vec[map_Address_to_L2Node(request.addr)]->enqueue(out_msg, 1); } } if(g_VARIANTE==13) PattsMetrics(); //stats for(i=0; i< numOfBanks; i++) { maxDemandQueueSize[i]<banks[i].demandQueue.size() ? maxDemandQueueSize[i]=banks[i].demandQueue.size() : 0; maxPrefetchQueueSize[i]<banks[i].prefetchQueue.size() ? maxPrefetchQueueSize[i]=banks[i].prefetchQueue.size() : 0; medDemandQueueSize[i]+=banks[i].demandQueue.size(); medPrefetchQueueSize[i]+=banks[i].prefetchQueue.size(); } }//dominio 1/4 prefQueueBank0.add(banks[0].prefetchQueue.size()); prefQueueBank1.add(banks[1].prefetchQueue.size()); int barrierBank=lastBankUsed; //i=firstBank(); //j=i; j = -1; bool reqServed=false; int reqType=-1; Time demTime=0, prefTime=0; //para averiguar quiŽn lleg— antes al controlador bool alldemands=false; //cerr << "wakeup DRAM: " << g_eventQueue_ptr->getTime() << endl; bool oldestTry = false; while(!reqServed && j!=barrierBank) { //cerr << "bucle achedule" << endl; reqType=-1; //This first part of the conditional tries to schedule the oldest queued request if(!oldestTry) { oldestTry = true; Time oldestTime = 0; int oldestIndex = -1; for(int auxIndex=0; auxIndex < numOfBanks; auxIndex++) { if(banks[auxIndex].demandQueue.size()>0) { Time auxTime = banks[auxIndex].demandQueue.front().queueTime; if(auxTime < oldestTime || oldestTime==0) { oldestTime = auxTime; oldestIndex = auxIndex; } } } if(oldestIndex != -1) { reqType = 1; i = oldestIndex; j=(oldestIndex==numOfBanks-1)?0:oldestIndex+1; } else { i=firstBank(); j=i; continue; } } else { while(reqType==-1 && j!=barrierBank && !alldemands ) { //cout << "buc 1a barrier" << barrierBank << " i: " << i << " j: " << j << endl; if(banks[j].demandQueue.size()>0) { reqType=1; i=j; j=(j==numOfBanks-1)?0:j+1; goto salida1; } //siguiente banco % #bancos j=(j==numOfBanks-1)?0:j+1; if(j==barrierBank) alldemands=true; //cout << "buc 1b barrier" << barrierBank << " i: " << i << " j: " << j << endl; } if(j==barrierBank) j=(j==numOfBanks-1)?0:j+1; while(reqType==-1) { //cout << "buc 2a barrier" << barrierBank << " i: " << i << " j: " << j << endl; //cout << "i: " << i << " j: " << j << "size: " << banks[j].prefetchQueue.size() << endl; if(banks[j].prefetchQueue.size()>0) { reqType=0; i=j; j=(j==numOfBanks-1)?0:j+1; goto salida1; } //siguiente banco % #bancos j=(j==numOfBanks-1)?0:j+1; if(j==barrierBank) break; //cout << "buc 2b barrier" << barrierBank << " i: " << i << " j: " << j << endl; } if(reqType==-1 || j==barrierBank) { g_eventQueue_ptr->scheduleEvent(this, 1); return; } } salida1: //------- Hasta aqu’ el c—digo que marca la prioridad request=(reqType ? banks[i].demandQueue : banks[i].prefetchQueue).front(); //comparamos la p‡gina que abri— el banco la œltima vez con la de la petici—n que vamos a servir //if(i==2) cout << "req.addr: " << getPage(request.addr.getAddress()) << " bank.pag: " << banks[i].pageTAG << endl; hit= getPage(request.addr.getAddress())==banks[i].pageTAG; // if(DEBUG_DRAM && !g_CARGA_CACHE)cout << "antes: \t\t" << binary(busBusyBitmap) << endl; if(!(busBusyBitmap & (hit ? (request.write ? Dram::writeHitBusBusyMask : Dram::readHitBusBusyMask) \ : (request.write ? Dram::writeMissBusBusyMask : Dram::readMissBusBusyMask)))) //si el bus puede estar libre para la petici—n elegida if(!(banks[i].bankBusyBitmap & (hit ? (request.write ? Dram::writeHitBankBusyMask : Dram::readHitBankBusyMask) \ : (request.write ? Dram::writeMissBankBusyMask : Dram::readMissBankBusyMask)))) //si el banco puede estar libre para la petici—n elegida { //cerr << "core: " << request.core << "\t" << " bank: "<< i << "\t" << (request.write ? "W" : "R") << (hit ? "\thit" : "\tmiss") << endl; //la petici—n puede ser servida //actualizamos tablas de ocupaci—n if(request.write) busBusyBitmap |= (hit ? writeHitBusBusyMask : writeMissBusBusyMask); else busBusyBitmap |= (hit ? readHitBusBusyMask : readMissBusBusyMask); //if(DEBUG_DRAM && !g_CARGA_CACHE) //cout << "despues: \t" << binary(busBusyBitmap) << "\t" << busBusyBitmap << endl; if(request.write) banks[i].bankBusyBitmap |= (hit ? writeHitBankBusyMask : writeMissBankBusyMask); else banks[i].bankBusyBitmap |= (hit ? readHitBankBusyMask : readMissBankBusyMask); //actualizamos la p‡gina abierta en el banco if(!hit) banks[i].pageTAG= getPage(request.addr.getAddress()); //PattsMetrics //coresQueued[i][L1CacheMachIDToProcessorNum(request.core)]--; (reqType ? banks[i].demandQueue : banks[i].prefetchQueue).pop_front(); //Atenci—n si cambiamos la temporizaci—n!!!! if(!request.write) request.wakeUp= g_eventQueue_ptr->getTime() + freqRatio* (hit ? 19 : 34); else request.wakeUp= g_eventQueue_ptr->getTime() + freqRatio* (hit ? 12 : 28); //metemos la petici—n en el bus //******************************************************** //las peticiones est‡n ordenadas porque el bus es una cola con prioridad bus.push(request); //stats if(!request.write) cyclesBusBusyPerProc[L1CacheMachIDToProcessorNum(request.core)]+=g_CYCLES_BUS_DRAM; //********************************* //stats if(hit) (reqType ? numDemandPageHits[i] : numPrefetchPageHits[i])++; //num aciertos pag if(hit && request.secondMiss) numSecondMissPageHits[i]++; //num aciertos pag (reqType ? numDemandsServed[i] : numPrefetchsServed[i])++; //num servicios if(request.secondMiss) numSecondMissesServed[i]++; //cout << "lat Servicio:" << request.wakeUp - request.queueTime <<endl; uint64 aux=request.wakeUp - request.queueTime; uint64 aux2=reqType ? latDemandMax[i] : latPrefetchMax[i]; (reqType ? latDemandMax[i] : latPrefetchMax[i])= (aux2>aux ? aux2 : aux); aux2=reqType ? latDemandMin[i] : latPrefetchMin[i]; (reqType ? latDemandMin[i] : latPrefetchMin[i])= (aux2<aux ? aux2 : aux); (reqType ? cyclesDemandService[i] : cyclesPrefetchService[i])+= aux; //latencia servicio reqServed=true; lastBankUsed=i; DEBUG_SLICC(MedPrio, "DramController request programmed (address): ", request.addr); DEBUG_SLICC(MedPrio, "DramController request programmed (ReqType): ", reqType); DEBUG_SLICC(MedPrio, "DramController request programmed (hit): ", hit); DEBUG_SLICC(MedPrio, "DramController request programmed (queue): ", g_eventQueue_ptr->getTime()); DEBUG_SLICC(MedPrio, "DramController request programmed (wakeup): ", request.wakeUp); DEBUG_SLICC(MedPrio, "DramController request programmed (bank): ", i); } } //while reqServed //siguiente banco % #bancos g_eventQueue_ptr->scheduleEvent(this, 1); }//valid memory
bool TransactionConflictManager::shouldNackStore(Address addr, uint64 remote_timestamp, MachineID remote_id){ bool existConflict = false; int remote_proc = L1CacheMachIDToProcessorNum(remote_id); int remote_thread = 0; int remote_logical_proc_num = remote_proc * RubyConfig::numberofSMTThreads() + remote_thread; string conflict_res_policy(XACT_CONFLICT_RES); if (XACT_EAGER_CD && !XACT_LAZY_VM){ if (XACT_MGR->isInWriteFilterSummary(addr)){ for (int i = 0; i < RubyConfig::numberofSMTThreads(); i++){ setLowestConflictLevel(i, addr, true); } if (conflict_res_policy == "TIMESTAMP"){ assert(!OpalInterface::isOpalLoaded()); if (getTimestamp(0) >= remote_timestamp){ XACT_MGR->setAbortFlag(0, addr); if (ATMTP_ENABLED) { XACT_MGR->setCPS_coh(0); } setEnemyProcessor(0, remote_logical_proc_num); m_magicWaitingOn[0] = remote_logical_proc_num; m_magicWaitingTime[0] = remote_timestamp; m_needMagicWait[0] = true; // remove this addr from isolation checker if(XACT_ISOLATION_CHECK){ //cout << "REMOVING ADDR " << addr << " FROM READ SET OF " << getProcID() << endl; Address temp = addr; temp.makeLineAddress(); int transactionLevel = XACT_MGR->getTransactionLevel(0); for(int level=1; level<=transactionLevel; ++level){ g_system_ptr->getXactIsolationChecker()->removeFromWriteSet(getProcID(), temp, level); } } } } return true; } else if (XACT_MGR->isInReadFilterSummary(addr)){ for (int i = 0; i < RubyConfig::numberofSMTThreads(); i++){ setLowestConflictLevel(i, addr, true); } if (conflict_res_policy == "HYBRID" || conflict_res_policy == "TIMESTAMP"){ assert(!OpalInterface::isOpalLoaded()); if (getTimestamp(0) >= remote_timestamp){ XACT_MGR->setAbortFlag(0, addr); if (ATMTP_ENABLED) { XACT_MGR->setCPS_coh(0); } setEnemyProcessor(0, remote_logical_proc_num); // remove this addr from isolation checker if(XACT_ISOLATION_CHECK){ //cout << "REMOVING ADDR " << addr << " FROM READ SET OF " << getProcID() << endl; Address temp = addr; temp.makeLineAddress(); int transactionLevel = XACT_MGR->getTransactionLevel(0); for(int level=1; level<=transactionLevel; ++level){ g_system_ptr->getXactIsolationChecker()->removeFromReadSet(getProcID(), temp, level); } } return false; } else { return true; } } return true; } return false; } else if (XACT_EAGER_CD && XACT_LAZY_VM){ if (XACT_MGR->isInWriteFilterSummary(addr) || XACT_MGR->isInReadFilterSummary(addr)){ assert(!OpalInterface::isOpalLoaded()); if (XACT_MGR->isTokenOwner(0)) return true; if (conflict_res_policy == "BASE"){ int proc = getLogicalProcID(0); //cout << "Proc " << proc << " STORE SETTING ABORT FLAG PC = " << SIMICS_get_program_counter(proc) << " Remote Proc = " << remote_logical_proc_num << " RemotePC = " << SIMICS_get_program_counter(remote_logical_proc_num) << " addr = " << addr << endl; XACT_MGR->setAbortFlag(0, addr); if (ATMTP_ENABLED) { XACT_MGR->setCPS_coh(0); } setEnemyProcessor(0, remote_logical_proc_num); // remove this addr from isolation checker if(XACT_ISOLATION_CHECK){ //cout << "REMOVING ADDR " << addr << " FROM READ SET OF " << getProcID() << endl; Address temp = addr; temp.makeLineAddress(); if(XACT_MGR->isInWriteFilterSummary(addr)){ int transactionLevel = XACT_MGR->getTransactionLevel(0); for(int level=1; level<=transactionLevel; ++level){ g_system_ptr->getXactIsolationChecker()->removeFromWriteSet(getProcID(), temp, level); } } if(XACT_MGR->isInReadFilterSummary(addr)){ int transactionLevel = XACT_MGR->getTransactionLevel(0); for(int level=1; level<=transactionLevel; ++level){ g_system_ptr->getXactIsolationChecker()->removeFromReadSet(getProcID(), temp, level); } } } return false; } else if (conflict_res_policy == "TIMESTAMP"){ if (getTimestamp(0) >= remote_timestamp){ XACT_MGR->setAbortFlag(0, addr); if (ATMTP_ENABLED) { XACT_MGR->setCPS_coh(0); } setEnemyProcessor(0, remote_logical_proc_num); // remove this addr from isolation checker if(XACT_ISOLATION_CHECK){ //cout << "REMOVING ADDR " << addr << " FROM READ SET OF " << getProcID() << endl; Address temp = addr; temp.makeLineAddress(); if(XACT_MGR->isInWriteFilterSummary(addr)){ int transactionLevel = XACT_MGR->getTransactionLevel(0); for(int level=1; level<=transactionLevel; ++level){ g_system_ptr->getXactIsolationChecker()->removeFromWriteSet(getProcID(), temp, level); } } if(XACT_MGR->isInReadFilterSummary(addr)){ int transactionLevel = XACT_MGR->getTransactionLevel(0); for(int level=1; level<=transactionLevel; ++level){ g_system_ptr->getXactIsolationChecker()->removeFromReadSet(getProcID(), temp, level); } } } return false; } return true; } else if (conflict_res_policy == "CYCLE"){ return true; } else { assert(0); } } return false; } else { // for LL systems if (XACT_MGR->isInReadFilterSummary(addr) || XACT_MGR->isInWriteFilterSummary(addr)){ if (conflict_res_policy != "BASE"){ cout << "XACT_CONFLICT_RES: " << conflict_res_policy << endl; assert(0); } assert(!OpalInterface::isOpalLoaded()); if (XACT_MGR->isTokenOwner(0)) return true; if (XACT_MGR->isInReadFilterSummary(addr)){ XACT_MGR->setAbortFlag(0, addr); if (ATMTP_ENABLED) { XACT_MGR->setCPS_coh(0); } setEnemyProcessor(0, remote_logical_proc_num); } return false; } return false; } assert(0); return false; }
void profilePrefInv(MachineID mach, bool inst) { int proc_num = L1CacheMachIDToProcessorNum(mach); g_system_ptr->getProfiler()->addL1PrefInv(proc_num, inst); }