//**************************************************************************
//* LCD initialization
//**************************************************************************
//* Calling arguments:
//* char mode1 : display mode (number of lines and character size)
//* char mode2 : display mode (cursor and display state)
//**************************************************************************
void LCD_init(char mode1, char mode2)
{
char aux;
// Configure the pins as outputs
LCD_ENABLE_DIR = 1;
LCD_RS_DIR = 1;
LCD_D4_DIR = 1;
LCD_D5_DIR = 1;
LCD_D6_DIR = 1;
LCD_D7_DIR = 1;
// Set the LCD data pins to zero
LCD_D4 = 0;
LCD_D5 = 0;
LCD_D6 = 0;
LCD_D7 = 0;
LCD_RS = 0;
LCD_ENABLE = 0; // LCD enable = 0
LCD_delay_ms(15);
// LCD 4-bit mode initialization sequence
// send three times 0x03 and then 0x02 to finish configuring the LCD
for(aux=0;aux<3;++aux)
{
LCD_send_nibble(3);
LCD_delay_ms(5);
}
LCD_send_nibble(2);
// Now send the LCD configuration data
LCD_send_byte(0,0x20 | mode1);
LCD_send_byte(0,0x08 | mode2);
lcd_mode = 0x08 | mode2;
LCD_send_byte(0,1);
LCD_send_byte(0,6);
}
void lp079x01_exit(void)
{
spi_24bit_3wire(0x7000B7); //enter LP mode
spi_24bit_3wire(0x720342);
LCD_delay_ms(50);
spi_24bit_3wire(0x700028); //display off
LCD_delay_ms(10);
spi_24bit_3wire(0x700010); //sleep in cmd
LCD_delay_ms(20);
ssd2828_rst(0);
panel_rst(0);
}
static __s32 pwm_write_reg(__u32 offset, __u32 value)
{
sys_put_wvalue(gdisp.init_para.base_pwm + offset, value);
#ifdef CONFIG_ARCH_SUN4I
LCD_delay_ms(20);
#endif
return 0;
}
void vvx07h005a00_exit(void)
{
//spi_24bit_3wire(0x7000B7); //enter LP mode
//spi_24bit_3wire(0x720342);
//LCD_delay_ms(50);
//spi_24bit_3wire(0x700028); //display off
//LCD_delay_ms(10);
//spi_24bit_3wire(0x700010); //sleep in cmd
LCD_delay_ms(20);
ssd2828_rst(0);
//ssd2828_shutdown(0);
}
//**************************************************************************
//* Write a character on the display
//**************************************************************************
//* Calling arguments:
//* char c : character to be written
//**************************************************************************
//* Notes :
//* \f clear the display
//* \n and \r return the cursor to line 1 column 0
//**************************************************************************
void LCD_write_char(char c)
{
switch (c)
{
case '\f' :
LCD_send_byte(0,1);
LCD_delay_ms(5);
break;
case '\n' :
case '\r' :
LCD_pos_xy(0,1);
break;
default:
LCD_send_byte(1,c);
}
}
void LCD_write_string_row(const rom char *c) {
unsigned char i;
i = 0;
LCD_pos_xy(0, 2);
while (*c) {
LCDChar(*c++);
i++;
if (i == 16) {
LCD_pos_xy(0, 0);
}
if (i == 32) {
LCD_delay_ms(10);
LCD_pos_xy(0, 2);
i = 0;
}
}
}
void LCD_write_string2(char *c, int k) {
int i;
i = k;
if (i == 0) {
clear();
}
while (*c) {
LCDChar(*c++);
i++;
if (i == 16) {
Inicio_2Linha();
}
if (i == 32) {
LCD_delay_ms(10);
clear();
i = 0;
}
}
}
void vvx07h005a00_init(__panel_para_t * info)
{
spi_24bit_3wire(0x7000B7); //enter LP mode
spi_24bit_3wire(0x720340);
ssd2828_shutdown(1);
ssd2828_rst(0);
LCD_delay_ms(20);
ssd2828_rst(1);
spi_24bit_3wire(0x7000B1);
spi_24bit_3wire(0x720110);
spi_24bit_3wire(0x7000B2);
spi_24bit_3wire(0x720330);
spi_24bit_3wire(0x7000B3);
spi_24bit_3wire(0x720510);
spi_24bit_3wire(0x7000B4);
spi_24bit_3wire(0x720320);
spi_24bit_3wire(0x7000B5);
spi_24bit_3wire(0x720500);
spi_24bit_3wire(0x7000B6);
//spi_24bit_3wire(0x720007);
spi_24bit_3wire(0x72000A); //Burst mode
//////////////////////////
spi_24bit_3wire(0x7000C9);
spi_24bit_3wire(0x721e04);
spi_24bit_3wire(0x7000CA);
spi_24bit_3wire(0x722f04);
spi_24bit_3wire(0x7000CB);
spi_24bit_3wire(0x720228);
spi_24bit_3wire(0x7000CC);
spi_24bit_3wire(0x720f0f);
delayms(10);
////////////////////////////
spi_24bit_3wire(0x7000DE);
spi_24bit_3wire(0x720003);
spi_24bit_3wire(0x7000D6);
spi_24bit_3wire(0x720005);
spi_24bit_3wire(0x7000B9);
spi_24bit_3wire(0x720000);
delayms(10);
////////////////////////////
spi_24bit_3wire(0x7000BA);
spi_24bit_3wire(0x728012);//27M OSC 500/27M=18=dex(12)
spi_24bit_3wire(0x7000BB);
spi_24bit_3wire(0x72000a);
spi_24bit_3wire(0x7000B9);
spi_24bit_3wire(0x720001);
delayms(200);
////////////////////////////
spi_24bit_3wire(0x7000B8);
spi_24bit_3wire(0x720000);
spi_24bit_3wire(0x7000B7);
spi_24bit_3wire(0x720342);
delayms(10);
delayms(10);
//while(1)
{
////////////////////////////
spi_24bit_3wire(0x7000Bc);
spi_24bit_3wire(0x720000);
spi_24bit_3wire(0x700011);
delayms(10);
}
spi_24bit_3wire(0x7000Bc);
spi_24bit_3wire(0x720002);
spi_24bit_3wire(0x7000BF);
spi_24bit_3wire(0x720BAE);
delayms(10);
spi_24bit_3wire(0x7000BF);
spi_24bit_3wire(0x7202BE);
delayms(10);
spi_24bit_3wire(0x7000BF);
spi_24bit_3wire(0x7290B5);
delayms(10);
spi_24bit_3wire(0x7000BF);
spi_24bit_3wire(0x7209B6);
delayms(10);
////////////////////////////
spi_24bit_3wire(0x7000Bc);
spi_24bit_3wire(0x720000);
spi_24bit_3wire(0x700010);
delayms(10);
delayms(50);
spi_24bit_3wire(0x7000B7);
spi_24bit_3wire(0x72024B);//0x72024B
delayms(50);
// spi_24bit_3wire(0x7000c0);
// spi_24bit_3wire(0x720100);
/*
spi_24bit_3wire(0x7000Bc);
spi_24bit_3wire(0x720000);
spi_24bit_3wire(0x700010);
delayms(10);
*/
/*
spi_24bit_3wire(0x7000Bc);
spi_24bit_3wire(0x720000);
spi_24bit_3wire(0x700029);
delayms(10);
*/
////////////////////////////
}
void anx9804_init(__panel_para_t * info)
{
__u8 c;
__s32 i;
__u32 count = 0;
__u32 lanes;
__u32 data_rate;
__u32 colordepth;
lanes = info->lcd_edp_tx_lane;
data_rate = 0x06;
if(info->lcd_edp_tx_rate == 1)
{
data_rate = 0x06;//1.62G
}
else if(info->lcd_edp_tx_rate == 2)
{
data_rate = 0x0a;//2.7G
}
colordepth = (info->lcd_edp_colordepth == 1)? 0x00:0x10;//0x00: 6bit; 0x10:8bit
//HW reset
lcd_iic_write(0x72, DP_TX_RST_CTRL_REG, DP_TX_RST_HW_RST);
LCD_delay_ms(10);
lcd_iic_write(0x72, DP_TX_RST_CTRL_REG, 0x00);
//Power on total and select DP mode
lcd_iic_write(0x72, DP_POWERD_CTRL_REG, 0x00 );
//get chip ID. Make sure I2C is OK
lcd_iic_read(0x72, DP_TX_DEV_IDH_REG , &c);
if(c==0x98)
{
OSAL_PRINTF("ANX9804 Chip found\n");
}
else
{
OSAL_PRINTF("ANX9804 Chip not found\n");
}
#if 0
//for clock detect
for(i=0;i<50;i++)
{
lcd_iic_read(0x70, DP_TX_SYS_CTRL1_REG, &c);
lcd_iic_write(0x70, DP_TX_SYS_CTRL1_REG, c);
lcd_iic_read(0x70, DP_TX_SYS_CTRL1_REG, &c);
if((c&DP_TX_SYS_CTRL1_DET_STA)!=0)
{
OSAL_PRINTF("ANX9804 clock is detected.\n");
break;
}
LCD_delay_ms(10);
}
#endif
//check whether clock is stable
for(i=0;i<50;i++)
{
lcd_iic_read(0x70, DP_TX_SYS_CTRL2_REG, &c);
lcd_iic_write(0x70, DP_TX_SYS_CTRL2_REG, c);
lcd_iic_read(0x70, DP_TX_SYS_CTRL2_REG, &c);
if((c&DP_TX_SYS_CTRL2_CHA_STA)==0)
{
OSAL_PRINTF("ANX9804 clock is stable.\n");
break;
}
LCD_delay_ms(10);
}
//VESA range, 8bits BPC, RGB
lcd_iic_write(0x72, DP_TX_VID_CTRL2_REG, colordepth);
//ANX9804 chip analog setting
lcd_iic_write(0x70, DP_TX_PLL_CTRL_REG, 0x07);
lcd_iic_write(0x72, DP_TX_PLL_FILTER_CTRL3, 0x19);
lcd_iic_write(0x72, DP_TX_PLL_CTRL3, 0xd9);
//lcd_iic_write(0x7a, 0x38, 0x10);
//lcd_iic_write(0x7a, 0x39, 0x20);
//lcd_iic_write(0x7a, 0x65, 0x00);
//Select AC mode
lcd_iic_write(0x72, DP_TX_RST_CTRL2_REG, 0x40);
//lcd_iic_write(0x7a, 0x61, 0x10);
//lcd_iic_write(0x7a, 0x62, 0x10);
//lcd_iic_write(0x7a, 0x63, 0x10);
//lcd_iic_write(0x7a, 0x64, 0x10);
//ANX9804 chip analog setting
lcd_iic_write(0x72, ANALOG_DEBUG_REG1, 0xf0);
lcd_iic_write(0x72, ANALOG_DEBUG_REG3, 0x99);
lcd_iic_write(0x72, DP_TX_PLL_FILTER_CTRL1, 0x7b);
lcd_iic_write(0x70, DP_TX_LINK_DEBUG_REG, 0x30);
lcd_iic_write(0x72, DP_TX_PLL_FILTER_CTRL, 0x06);
//force HPD
lcd_iic_write(0x70, DP_TX_SYS_CTRL3_REG, 0x30);
//power on 4 lanes
lcd_iic_write(0x70, 0xc8, 0x00);
//lanes setting
lcd_iic_write(0x70, 0xa3, 0x00);
lcd_iic_write(0x70, 0xa4, 0x00);
lcd_iic_write(0x70, 0xa5, 0x00);
lcd_iic_write(0x70, 0xa6, 0x00);
#if 0
//step 1: read DPCD 0x00001, the correct value should be 0x0a, or 0x06
lcd_iic_write(0x70, 0xE4, 0x80);
//set read cmd and count, read 2 __u8s data, get downstream max_bandwidth and max_lanes
lcd_iic_write(0x70, 0xE5, 0x19);
//set aux address19:0
lcd_iic_write(0x70, 0xE6, 0x01);
lcd_iic_write(0x70, 0xE7, 0x00);
lcd_iic_write(0x70, 0xE8, 0x00);
//Enable Aux
lcd_iic_write(0x70, 0xE9, 0x01);
//wait aux finished
for(i=0; i<50; i++)
{
lcd_iic_read(0x70, 0xE9, &c);
if(c==0x00)
{
break;
}
}
//read data from buffer
lcd_iic_write( 0x70, 0xF0, &max_bandwidth);
lcd_iic_write( 0x70, 0xF1, &max_lanes);
debug_pr__s32f("max_bandwidth = %.2x, max_lanes = %.2x\n", (WORD)max_bandwidth, (WORD)max_lanes);
#endif
//reset AUX CH
lcd_iic_write(0x72, DP_TX_RST_CTRL2_REG, 0x44);
lcd_iic_write(0x72, DP_TX_RST_CTRL2_REG, 0x40);
//to save power
lcd_iic_write(0x72, DP_POWERD_CTRL_REG, 0x10 );//audio power down
lcd_iic_write(0x70, DP_TX_HDCP_CONTROL_0_REG, 0x00 );
lcd_iic_write(0x70, 0xA7, 0x00 );//Spread spectrum 30 kHz
//end
/* enable ssc function */
lcd_iic_write(0x70, 0xa7, 0x00); // disable SSC first
lcd_iic_write(0x70, 0xa0, 0x00); //disable speed first
lcd_iic_write(0x72, 0xde, 0x99); //set duty cycle
lcd_iic_read(0x70, 0xc7, &c); //reset DP PLL
lcd_iic_write(0x70, 0xc7, c & (~0x40));
lcd_iic_read(0x70, 0xd8, &c); //M value select, select clock with downspreading
lcd_iic_write(0x70, 0xd8, (c | 0x01));
lcd_iic_write(0x70, 0xc7, 0x02); //PLL power 1.7V
lcd_iic_write(0x70, 0xd0, 0xb8); // ssc d 0.5%
lcd_iic_write(0x70, 0xd1, 0x6D); // ctrl_th 30.4237K
lcd_iic_write(0x70, 0xa7, 0x10); // enable SSC
lcd_iic_read(0x72, 0x07, &c); //ssc reset
lcd_iic_write(0x72, 0x07, c | 0x80);
lcd_iic_write(0x72, 0x07, c & (~0x80));
//Select 2.7G
//lcd_iic_write(0x70, DP_TX_LINK_BW_SET_REG, 0x0a);
lcd_iic_write(0x70, DP_TX_LINK_BW_SET_REG, data_rate); //0x06: Select 1.62G
//Select 4 lanes
lcd_iic_write(0x70, DP_TX_LANE_COUNT_SET_REG, lanes);
//strart link traing
//DP_TX_LINK_TRAINING_CTRL_EN is self clear. If link training is OK, it will self cleared.
lcd_iic_write(0x70, DP_TX_LINK_TRAINING_CTRL_REG, DP_TX_LINK_TRAINING_CTRL_EN);
LCD_delay_ms(5);
lcd_iic_read(0x70, DP_TX_LINK_TRAINING_CTRL_REG, &c);
while((c&0x01)!=0)
{
OSAL_PRINTF("ANX9804 Waiting...\n");
LCD_delay_ms(5);
count ++;
if(count > 100)
{
OSAL_PRINTF("ANX9804 Link training fail\n");
break;
}
lcd_iic_read(0x70, DP_TX_LINK_TRAINING_CTRL_REG, &c);
}
//lcd_iic_write(0x7a, 0x7c, 0x02);
//BIST MODE: video format. In normal mode, don't need to config these reg from 0x12~0x21
//lcd_iic_write(0x72, 0x12, 0x2c);
//lcd_iic_write(0x72, 0x13, 0x06);
//lcd_iic_write(0x72, 0x14, 0x00);
//lcd_iic_write(0x72, 0x15, 0x06);
//lcd_iic_write(0x72, 0x16, 0x02);
//lcd_iic_write(0x72, 0x17, 0x04);
//lcd_iic_write(0x72, 0x18, 0x26);
//lcd_iic_write(0x72, 0x19, 0x50);
//lcd_iic_write(0x72, 0x1a, 0x04);
//lcd_iic_write(0x72, 0x1b, 0x00);
//lcd_iic_write(0x72, 0x1c, 0x04);
//lcd_iic_write(0x72, 0x1d, 0x18);
//lcd_iic_write(0x72, 0x1e, 0x00);
//lcd_iic_write(0x72, 0x1f, 0x10);
//lcd_iic_write(0x72, 0x20, 0x00);
//lcd_iic_write(0x72, 0x21, 0x28);
//lcd_iic_write(0x72, 0x11, 0x03);
//enable BIST. In normal mode, don't need to config this reg
//lcd_iic_write(0x72, 0x0b, 0x08);
//enable video input, set DDR mode, the input DCLK should be 102.5MHz;
//In normal mode, set this reg to 0x81, SDR mode, the input DCLK should be 205MHz
//lcd_iic_write(0x72, 0x08, 0x8d);
//lcd_iic_write(0x72, 0x08, 0x81);
lcd_iic_write(0x72, 0x08, 0x81);
//force HPD and stream valid
lcd_iic_write(0x70, 0x82, 0x33);
}
static void
Lcd_Panel_Parameter_Check(__u32 sel)
{
__panel_para_t *info;
__u32 cycle_num = 1;
__u32 Lcd_Panel_Err_Flag = 0;
__u32 Lcd_Panel_Wrn_Flag = 0;
__u32 Disp_Driver_Bug_Flag = 0;
__u32 lcd_fclk_frq;
__u32 lcd_clk_div;
info = &(gpanel_info[sel]);
if (info->lcd_if == 0 && info->lcd_hv_if == 1 &&
info->lcd_hv_smode == 0)
cycle_num = 3;
else if (info->lcd_if == 0 && info->lcd_hv_if == 1 &&
info->lcd_hv_smode == 1)
cycle_num = 2;
else if (info->lcd_if == 1 && info->lcd_cpu_if == 1)
cycle_num = 3;
else if (info->lcd_if == 1 && info->lcd_cpu_if == 2)
cycle_num = 2;
else if (info->lcd_if == 1 && info->lcd_cpu_if == 3)
cycle_num = 2;
else if (info->lcd_if == 1 && info->lcd_cpu_if == 5)
cycle_num = 2;
else if (info->lcd_if == 1 && info->lcd_cpu_if == 6)
cycle_num = 3;
else if (info->lcd_if == 1 && info->lcd_cpu_if == 7)
cycle_num = 2;
else
cycle_num = 1;
if (info->lcd_hbp > info->lcd_hv_hspw)
;
else
Lcd_Panel_Err_Flag |= BIT0;
if (info->lcd_vbp > info->lcd_hv_vspw)
;
else
Lcd_Panel_Err_Flag |= BIT1;
if (info->lcd_ht >= (info->lcd_hbp + info->lcd_x * cycle_num + 4))
;
else
Lcd_Panel_Err_Flag |= BIT2;
if ((info->lcd_vt / 2) >= (info->lcd_vbp + info->lcd_y + 2))
;
else
Lcd_Panel_Err_Flag |= BIT3;
lcd_clk_div = TCON0_get_dclk_div(sel);
if (lcd_clk_div >= 6) {
;
} else if ((lcd_clk_div == 5) || (lcd_clk_div == 4) ||
(lcd_clk_div == 2)) {
if ((info->lcd_io_cfg0 != 0x00000000) &&
(info->lcd_io_cfg0 != 0x04000000))
Lcd_Panel_Err_Flag |= BIT10;
} else
Disp_Driver_Bug_Flag |= 1;
if ((info->lcd_if == 1 && info->lcd_cpu_if == 0) ||
(info->lcd_if == 3 && info->lcd_lvds_bitwidth == 1)) {
if (info->lcd_frm != 1)
Lcd_Panel_Wrn_Flag |= BIT0;
} else if (info->lcd_if == 1 && info->lcd_cpu_if == 4) {
if (info->lcd_frm != 2)
Lcd_Panel_Wrn_Flag |= BIT1;
}
lcd_fclk_frq = (info->lcd_dclk_freq * 1000 * 1000) /
((info->lcd_vt / 2) * info->lcd_ht);
if (lcd_fclk_frq < 50 || lcd_fclk_frq > 70)
Lcd_Panel_Wrn_Flag |= BIT2;
if (Lcd_Panel_Err_Flag != 0 || Lcd_Panel_Wrn_Flag != 0) {
if (Lcd_Panel_Err_Flag != 0) {
__u32 i;
for (i = 0; i < 200; i++)
DE_WRN("*** Lcd in danger...\n");
}
DE_WRN("*******************************************************"
"**********\n");
DE_WRN("***\n");
DE_WRN("*** LCD Panel Parameter Check\n");
DE_WRN("***\n");
DE_WRN("*** by dulianping\n");
DE_WRN("***\n");
DE_WRN("*******************************************************"
"**********\n");
DE_WRN("***\n");
DE_WRN("*** Interface:");
if (info->lcd_if == 0 && info->lcd_hv_if == 0) {
DE_WRN("*** Parallel HV Panel\n");
} else if (info->lcd_if == 0 && info->lcd_hv_if == 1) {
DE_WRN("*** Serial HV Panel\n");
} else if (info->lcd_if == 0 && info->lcd_hv_if == 2) {
DE_WRN("*** Serial YUV Panel\n");
} else if (info->lcd_if == 3 && info->lcd_lvds_bitwidth == 0) {
DE_WRN("*** 24Bit LVDS Panel\n");
} else if (info->lcd_if == 3 && info->lcd_lvds_bitwidth == 1) {
DE_WRN("*** 18Bit LVDS Panel\n");
} else if (info->lcd_if == 1 && info->lcd_cpu_if == 0) {
DE_WRN("*** 18Bit CPU Panel\n");
} else if (info->lcd_if == 1 && info->lcd_cpu_if == 4) {
DE_WRN("*** 16Bit CPU Panel\n");
} else {
DE_WRN("\n");
DE_WRN("*** lcd_if: %d\n", info->lcd_if);
DE_WRN("*** lcd_hv_if: %d\n", info->lcd_hv_if);
DE_WRN("*** lcd_cpu_if: %d\n", info->lcd_cpu_if);
}
if (info->lcd_frm == 0)
DE_WRN("*** Lcd Frm Disable\n");
else if (info->lcd_frm == 1)
DE_WRN("*** Lcd Frm to RGB666\n");
else if (info->lcd_frm == 2)
DE_WRN("*** Lcd Frm to RGB565\n");
DE_WRN("***\n");
DE_WRN("*** Timing:\n");
DE_WRN("*** lcd_x: %d\n", info->lcd_x);
DE_WRN("*** lcd_y: %d\n", info->lcd_y);
DE_WRN("*** lcd_ht: %d\n", info->lcd_ht);
DE_WRN("*** lcd_hbp: %d\n", info->lcd_hbp);
DE_WRN("*** lcd_vt: %d\n", info->lcd_vt);
DE_WRN("*** lcd_vbp: %d\n", info->lcd_vbp);
DE_WRN("*** lcd_hspw: %d\n", info->lcd_hv_hspw);
DE_WRN("*** lcd_vspw: %d\n", info->lcd_hv_vspw);
DE_WRN("*** lcd_frame_frq: %dHz\n", lcd_fclk_frq);
/* Print Error */
DE_WRN("***\n");
if (Lcd_Panel_Err_Flag & BIT0)
DE_WRN("*** Err01: Violate \"lcd_hbp > lcd_hspw\"\n");
if (Lcd_Panel_Err_Flag & BIT1)
DE_WRN("*** Err02: Violate \"lcd_vbp > lcd_vspw\"\n");
if (Lcd_Panel_Err_Flag & BIT2)
DE_WRN("*** Err03: Violate \"lcd_ht >= "
"(lcd_hbp+lcd_x*%d+4)\"\n", cycle_num);
if (Lcd_Panel_Err_Flag & BIT3)
DE_WRN("*** Err04: Violate \"(lcd_vt/2) >= "
"(lcd_vbp+lcd_y+2)\"\n");
if (Lcd_Panel_Err_Flag & BIT10)
DE_WRN("*** Err10: Violate \"lcd_io_cfg0\", "
"use \"0x00000000\" or \"0x04000000\"");
if (Lcd_Panel_Wrn_Flag & BIT0)
DE_WRN("*** WRN01: Recommend \"lcd_frm = 1\"\n");
if (Lcd_Panel_Wrn_Flag & BIT1)
DE_WRN("*** WRN02: Recommend \"lcd_frm = 2\"\n");
if (Lcd_Panel_Wrn_Flag & BIT2)
DE_WRN("*** WRN03: Recommend \"lcd_dclk_frq = %d\"\n",
((info->lcd_vt / 2) * info->lcd_ht) * 60 /
(1000 * 1000));
DE_WRN("***\n");
if (Lcd_Panel_Err_Flag != 0) {
__u32 image_base_addr;
__u32 reg_value = 0;
image_base_addr = DE_Get_Reg_Base(sel);
/* set background color */
sys_put_wvalue(image_base_addr + 0x804, 0xffff00ff);
reg_value = sys_get_wvalue(image_base_addr + 0x800);
/* close all layer */
sys_put_wvalue(image_base_addr + 0x800,
reg_value & 0xfffff0ff);
LCD_delay_ms(2000);
/* set background color */
sys_put_wvalue(image_base_addr + 0x804, 0x00000000);
/* open layer */
sys_put_wvalue(image_base_addr + 0x800, reg_value);
DE_WRN("*** Try new parameters, you can make it "
"pass!\n");
}
DE_WRN("*** LCD Panel Parameter Check End\n");
DE_WRN("*******************************************************"
"**********\n");
}
}
void lp079x01_init(__panel_para_t * info)
{
__u32 pll_config = 0;
if(info->lcd_xtal_freq == 12)
{
/* 12M xtal freq */
pll_config = 0xc02D;
} else if(info->lcd_xtal_freq == 27)
{
pll_config = 0xc014;
} else if(info->lcd_xtal_freq == 24)
{
pll_config = 0xc22d;
} else
{
/* default 12Mhz */
pll_config = 0xc02D;
}
spi_24bit_3wire(0x7000B7); //enter LP mode
spi_24bit_3wire(0x720340);
ssd2828_rst(0);
panel_rst(0);
LCD_delay_ms(10);
ssd2828_rst(1);
panel_rst(1);
LCD_delay_ms(10);
spi_24bit_3wire(0x7000B1); //VSA=50, HAS=64
spi_24bit_3wire(0x723240);
spi_24bit_3wire(0x7000B2); //VBP=30+50, HBP=56+64
spi_24bit_3wire(0x725078);
spi_24bit_3wire(0x7000B3); //VFP=36, HFP=60
spi_24bit_3wire(0x72243C);
spi_24bit_3wire(0x7000B4); //HACT=768
spi_24bit_3wire(0x720300);
spi_24bit_3wire(0x7000B5); //VACT=1240
spi_24bit_3wire(0x720400);
spi_24bit_3wire(0x7000B6);
if(info->lcd_ext_dsi_colordepth == 1) {
spi_24bit_3wire(0x720009); //0x720009:burst mode, 18bpp packed
} else {
spi_24bit_3wire(0x72000B); //0x72000B:burst mode, 24bpp
}
//0x72000A:burst mode, 18bpp loosely packed
spi_24bit_3wire(0x7000DE); //no of lane=4
spi_24bit_3wire(0x720003);
spi_24bit_3wire(0x7000D6); //RGB order and packet number in blanking period
spi_24bit_3wire(0x720005);
spi_24bit_3wire(0x7000B9); //disable PLL
spi_24bit_3wire(0x720000);
pll_config |= 0x720000;
pr_warn("[MINI]pll_config=0x%x\n", pll_config);
spi_24bit_3wire(0x7000BA); //lane speed=560
spi_24bit_3wire(pll_config); //may modify according to requirement, 500Mbps to 560Mbps, clk_in / (bit12-8) * (bit7-0)
spi_24bit_3wire(0x7000BB); //LP clock
spi_24bit_3wire(0x720008);
spi_24bit_3wire(0x7000B9); //enable PPL
spi_24bit_3wire(0x720001);
spi_24bit_3wire(0x7000c4); //enable BTA
spi_24bit_3wire(0x720001);
spi_24bit_3wire(0x7000B7); //enter LP mode
spi_24bit_3wire(0x720342);
spi_24bit_3wire(0x7000B8); //VC
spi_24bit_3wire(0x720000);
spi_24bit_3wire(0x7000BC); //set packet size
spi_24bit_3wire(0x720000);
spi_24bit_3wire(0x700011); //sleep out cmd
LCD_delay_ms(100);
spi_24bit_3wire(0x700029); //display on
LCD_delay_ms(200);
spi_24bit_3wire(0x7000B7); //video mode on
spi_24bit_3wire(0x72030b);
}
static void kgm281i0_init(__u32 sel)
{
kgm281i0_rs(sel,1);
LCD_delay_ms(50);
kgm281i0_rs(sel,0);
LCD_delay_ms(50);
kgm281i0_rs(sel,1);
LCD_CPU_WR(sel,0x0000, 0x0001);
LCD_CPU_WR(sel,0x0001, 0x0100);
LCD_CPU_WR(sel,0x0002, 0x0400);
LCD_CPU_WR(sel,0x0003, 0x1018);
LCD_CPU_WR(sel,0x0004, 0x0000);
LCD_CPU_WR(sel,0x0008, 0x0202);
LCD_CPU_WR(sel,0x0009, 0x0000);
LCD_CPU_WR(sel,0x000A, 0x0000);
LCD_CPU_WR(sel,0x000C, 0x0000);
LCD_CPU_WR(sel,0x000D, 0x0000);
LCD_CPU_WR(sel,0x000F, 0x0000);
LCD_CPU_WR(sel,0x0010, 0x0000);
LCD_CPU_WR(sel,0x0011, 0x0007);
LCD_CPU_WR(sel,0x0012, 0x0000);
LCD_CPU_WR(sel,0x0013, 0x0000);
LCD_delay_ms(50);
LCD_CPU_WR(sel,0x0010, 0x17B0);
LCD_CPU_WR(sel,0x0011, 0x0001);
LCD_delay_ms(50);
LCD_CPU_WR(sel,0x0012, 0x013C);
LCD_delay_ms(50);
LCD_CPU_WR(sel,0x0013, 0x1300);
LCD_CPU_WR(sel,0x0029, 0x0012);
LCD_delay_ms(50);
LCD_CPU_WR(sel,0x0020, 0x0000);
LCD_CPU_WR(sel,0x0021, 0x0000);
LCD_CPU_WR(sel,0x002B, 0x0020);
LCD_CPU_WR(sel,0x0030, 0x0000);
LCD_CPU_WR(sel,0x0031, 0x0306);
LCD_CPU_WR(sel,0x0032, 0x0200);
LCD_CPU_WR(sel,0x0035, 0x0107);
LCD_CPU_WR(sel,0x0036, 0x0404);
LCD_CPU_WR(sel,0x0037, 0x0606);
LCD_CPU_WR(sel,0x0038, 0x0105);
LCD_CPU_WR(sel,0x0039, 0x0707);
LCD_CPU_WR(sel,0x003C, 0x0600);
LCD_CPU_WR(sel,0x003D, 0x0807);
LCD_CPU_WR(sel,0x0050, 0x0000);
LCD_CPU_WR(sel,0x0051, 0x00EF);
LCD_CPU_WR(sel,0x0052, 0x0000);
LCD_CPU_WR(sel,0x0053, 0x013F);
LCD_CPU_WR(sel,0x0060, 0x2700);
LCD_CPU_WR(sel,0x0061, 0x0001);
LCD_CPU_WR(sel,0x006A, 0x0000);
LCD_CPU_WR(sel,0x0080, 0x0000);
LCD_CPU_WR(sel,0x0081, 0x0000);
LCD_CPU_WR(sel,0x0082, 0x0000);
LCD_CPU_WR(sel,0x0083, 0x0000);
LCD_CPU_WR(sel,0x0084, 0x0000);
LCD_CPU_WR(sel,0x0085, 0x0000);
LCD_CPU_WR(sel,0x0090, 0x0013);
LCD_CPU_WR(sel,0x0092, 0x0000);
LCD_CPU_WR(sel,0x0093, 0x0003);
LCD_CPU_WR(sel,0x0095, 0x0110);
LCD_CPU_WR(sel,0x0097, 0x0000);
LCD_CPU_WR(sel,0x0098, 0x0000);
LCD_CPU_WR(sel,0x0007, 0x0001);
LCD_delay_ms(50);
LCD_CPU_WR(sel,0x0007, 0x0021);
LCD_CPU_WR(sel,0x0007, 0x0023);
LCD_delay_ms(50);
LCD_CPU_WR(sel,0x0007, 0x0173);
}
void vvx07h005a00_init(__panel_para_t * info)
{
__u32 pll_config = 0;
if(info->lcd_xtal_freq == 12)
{
/* 12M xtal freq */
pll_config = 0xc02D;
} else if(info->lcd_xtal_freq == 27)
{
pll_config = 0xc013;
} else if(info->lcd_xtal_freq == 24)
{
pll_config = 0xc22d;
} else
{
/* default 12Mhz */
pll_config = 0xc02D;
}
ssd2828_shutdown(1);
//spi_24bit_3wire(0x7000B7); //enter LP mode
//spi_24bit_3wire(0x720340);
ssd2828_rst(0);
LCD_delay_ms(10);
ssd2828_rst(1);
spi_24bit_3wire(0x7000B1);
spi_24bit_3wire(0x720110);
spi_24bit_3wire(0x7000B2);
spi_24bit_3wire(0x720330);
spi_24bit_3wire(0x7000B3);
spi_24bit_3wire(0x720510);
spi_24bit_3wire(0x7000B4);
spi_24bit_3wire(0x720320);
spi_24bit_3wire(0x7000B5);
spi_24bit_3wire(0x720500);
spi_24bit_3wire(0x7000B6);
//spi_24bit_3wire(0x720007);
spi_24bit_3wire(0x72000A); //Burst mode
//////////////////////////
spi_24bit_3wire(0x7000C9);
spi_24bit_3wire(0x721e04);
spi_24bit_3wire(0x7000CA);
spi_24bit_3wire(0x722f04);
spi_24bit_3wire(0x7000CB);
spi_24bit_3wire(0x720228);
spi_24bit_3wire(0x7000CC);
spi_24bit_3wire(0x720f0f);
delayms(10);
////////////////////////////
spi_24bit_3wire(0x7000DE);
spi_24bit_3wire(0x720003);
spi_24bit_3wire(0x7000D6);
spi_24bit_3wire(0x720005);
spi_24bit_3wire(0x7000B9);
spi_24bit_3wire(0x720000);
delayms(10);
////////////////////////////
spi_24bit_3wire(0x7000BA);
spi_24bit_3wire(0x728012);//27M OSC 500/27M=18=dex(12)
spi_24bit_3wire(0x7000BB);
spi_24bit_3wire(0x72000a);
spi_24bit_3wire(0x7000B9);
spi_24bit_3wire(0x720001);
delayms(200);
////////////////////////////
spi_24bit_3wire(0x7000B8);
spi_24bit_3wire(0x720000);
spi_24bit_3wire(0x7000B7);
spi_24bit_3wire(0x720342);
delayms(10);
delayms(10);
//while(1)
{
////////////////////////////
spi_24bit_3wire(0x7000Bc);
spi_24bit_3wire(0x720000);
spi_24bit_3wire(0x700011);
delayms(10);
}
spi_24bit_3wire(0x7000Bc);
spi_24bit_3wire(0x720002);
spi_24bit_3wire(0x7000BF);
spi_24bit_3wire(0x720BAE);
delayms(10);
spi_24bit_3wire(0x7000BF);
spi_24bit_3wire(0x7202BE);
delayms(10);
spi_24bit_3wire(0x7000BF);
spi_24bit_3wire(0x7290B5);
delayms(10);
spi_24bit_3wire(0x7000BF);
spi_24bit_3wire(0x7209B6);
delayms(10);
////////////////////////////
spi_24bit_3wire(0x7000Bc);
spi_24bit_3wire(0x720000);
spi_24bit_3wire(0x700010);
delayms(10);
delayms(50);
spi_24bit_3wire(0x7000B7);
spi_24bit_3wire(0x72024B);//0x72024B
delayms(50);
// spi_24bit_3wire(0x7000c0);
// spi_24bit_3wire(0x720100);
/*
spi_24bit_3wire(0x7000Bc);
spi_24bit_3wire(0x720000);
spi_24bit_3wire(0x700010);
delayms(10);
*/
/*
spi_24bit_3wire(0x7000Bc);
spi_24bit_3wire(0x720000);
spi_24bit_3wire(0x700029);
delayms(10);
*/
////////////////////////////
}
