示例#1
0
static void
i915_init_packets(struct i915_context *i915)
{
   /* Zero all state */
   memset(&i915->state, 0, sizeof(i915->state));


   {
      I915_STATECHANGE(i915, I915_UPLOAD_CTX);
      I915_STATECHANGE(i915, I915_UPLOAD_BLEND);
      /* Probably don't want to upload all this stuff every time one 
       * piece changes.
       */
      i915->state.Ctx[I915_CTXREG_LI] = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
                                         I1_LOAD_S(2) |
                                         I1_LOAD_S(4) |
                                         I1_LOAD_S(5) | I1_LOAD_S(6) | (3));
      i915->state.Ctx[I915_CTXREG_LIS2] = 0;
      i915->state.Ctx[I915_CTXREG_LIS4] = 0;
      i915->state.Ctx[I915_CTXREG_LIS5] = 0;

      if (i915->intel.ctx.Visual.rgbBits == 16)
         i915->state.Ctx[I915_CTXREG_LIS5] |= S5_COLOR_DITHER_ENABLE;


      i915->state.Ctx[I915_CTXREG_LIS6] = (S6_COLOR_WRITE_ENABLE |
                                           (2 << S6_TRISTRIP_PV_SHIFT));

      i915->state.Ctx[I915_CTXREG_STATE4] = (_3DSTATE_MODES_4_CMD |
                                             ENABLE_LOGIC_OP_FUNC |
                                             LOGIC_OP_FUNC(LOGICOP_COPY) |
                                             ENABLE_STENCIL_TEST_MASK |
                                             STENCIL_TEST_MASK(0xff) |
                                             ENABLE_STENCIL_WRITE_MASK |
                                             STENCIL_WRITE_MASK(0xff));

      i915->state.Blend[I915_BLENDREG_IAB] =
         (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD | IAB_MODIFY_ENABLE |
          IAB_MODIFY_FUNC | IAB_MODIFY_SRC_FACTOR | IAB_MODIFY_DST_FACTOR);

      i915->state.Blend[I915_BLENDREG_BLENDCOLOR0] =
         _3DSTATE_CONST_BLEND_COLOR_CMD;
      i915->state.Blend[I915_BLENDREG_BLENDCOLOR1] = 0;

      i915->state.Ctx[I915_CTXREG_BF_STENCIL_MASKS] =
	 _3DSTATE_BACKFACE_STENCIL_MASKS |
	 BFM_ENABLE_STENCIL_TEST_MASK |
	 BFM_ENABLE_STENCIL_WRITE_MASK |
	 (0xff << BFM_STENCIL_WRITE_MASK_SHIFT) |
	 (0xff << BFM_STENCIL_TEST_MASK_SHIFT);
      i915->state.Ctx[I915_CTXREG_BF_STENCIL_OPS] =
	 _3DSTATE_BACKFACE_STENCIL_OPS |
	 BFO_ENABLE_STENCIL_REF |
	 BFO_ENABLE_STENCIL_FUNCS |
	 BFO_ENABLE_STENCIL_TWO_SIDE;
   }

   {
      I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
      i915->state.Stipple[I915_STPREG_ST0] = _3DSTATE_STIPPLE;
   }

   {
      i915->state.Buffer[I915_DESTREG_DV0] = _3DSTATE_DST_BUF_VARS_CMD;

      /* scissor */
      i915->state.Buffer[I915_DESTREG_SENABLE] =
         (_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
      i915->state.Buffer[I915_DESTREG_SR0] = _3DSTATE_SCISSOR_RECT_0_CMD;
      i915->state.Buffer[I915_DESTREG_SR1] = 0;
      i915->state.Buffer[I915_DESTREG_SR2] = 0;
   }

   i915->state.RasterRules[I915_RASTER_RULES] = _3DSTATE_RASTER_RULES_CMD |
      ENABLE_POINT_RASTER_RULE |
      OGL_POINT_RASTER_RULE |
      ENABLE_LINE_STRIP_PROVOKE_VRTX |
      ENABLE_TRI_FAN_PROVOKE_VRTX |
      LINE_STRIP_PROVOKE_VRTX(1) |
      TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D;

#if 0
   {
      I915_STATECHANGE(i915, I915_UPLOAD_DEFAULTS);
      i915->state.Default[I915_DEFREG_C0] = _3DSTATE_DEFAULT_DIFFUSE;
      i915->state.Default[I915_DEFREG_C1] = 0;
      i915->state.Default[I915_DEFREG_S0] = _3DSTATE_DEFAULT_SPECULAR;
      i915->state.Default[I915_DEFREG_S1] = 0;
      i915->state.Default[I915_DEFREG_Z0] = _3DSTATE_DEFAULT_Z;
      i915->state.Default[I915_DEFREG_Z1] = 0;
   }
#endif


   /* These will be emitted every at the head of every buffer, unless
    * we get hardware contexts working.
    */
   i915->state.active = (I915_UPLOAD_PROGRAM |
                         I915_UPLOAD_STIPPLE |
                         I915_UPLOAD_CTX |
                         I915_UPLOAD_BLEND |
                         I915_UPLOAD_BUFFERS |
			 I915_UPLOAD_INVARIENT |
			 I915_UPLOAD_RASTER_RULES);
}
static void
copy(int fd, uint32_t dst, uint32_t src)
{
	uint32_t batch[1024], *b = batch;
	struct drm_i915_gem_relocation_entry reloc[2], *r = reloc;
	struct drm_i915_gem_exec_object2 obj[3];
	struct drm_i915_gem_execbuffer2 exec;
	uint32_t handle;
	int ret;

	/* invariant state */
	*b++ = (_3DSTATE_AA_CMD |
		AA_LINE_ECAAR_WIDTH_ENABLE |
		AA_LINE_ECAAR_WIDTH_1_0 |
		AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
	*b++ = (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
		IAB_MODIFY_ENABLE |
		IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
		IAB_MODIFY_SRC_FACTOR | (BLENDFACT_ONE <<
					 IAB_SRC_FACTOR_SHIFT) |
		IAB_MODIFY_DST_FACTOR | (BLENDFACT_ZERO <<
					 IAB_DST_FACTOR_SHIFT));
	*b++ = (_3DSTATE_DFLT_DIFFUSE_CMD);
	*b++ = (0);
	*b++ = (_3DSTATE_DFLT_SPEC_CMD);
	*b++ = (0);
	*b++ = (_3DSTATE_DFLT_Z_CMD);
	*b++ = (0);
	*b++ = (_3DSTATE_COORD_SET_BINDINGS |
		CSB_TCB(0, 0) |
		CSB_TCB(1, 1) |
		CSB_TCB(2, 2) |
		CSB_TCB(3, 3) |
		CSB_TCB(4, 4) |
		CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
	*b++ = (_3DSTATE_RASTER_RULES_CMD |
		ENABLE_POINT_RASTER_RULE |
		OGL_POINT_RASTER_RULE |
		ENABLE_LINE_STRIP_PROVOKE_VRTX |
		ENABLE_TRI_FAN_PROVOKE_VRTX |
		LINE_STRIP_PROVOKE_VRTX(1) |
		TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D);
	*b++ = (_3DSTATE_MODES_4_CMD |
		ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
		ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
		ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));
	*b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | I1_LOAD_S(4) | I1_LOAD_S(5) | 2);
	*b++ = (0x00000000);	/* Disable texture coordinate wrap-shortest */
	*b++ = ((1 << S4_POINT_WIDTH_SHIFT) |
		S4_LINE_WIDTH_ONE |
		S4_CULLMODE_NONE |
		S4_VFMT_XY);
	*b++ = (0x00000000);	/* Stencil. */
	*b++ = (_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
	*b++ = (_3DSTATE_SCISSOR_RECT_0_CMD);
	*b++ = (0);
	*b++ = (0);
	*b++ = (_3DSTATE_DEPTH_SUBRECT_DISABLE);
	*b++ = (_3DSTATE_LOAD_INDIRECT | 0);	/* disable indirect state */
	*b++ = (0);
	*b++ = (_3DSTATE_STIPPLE);
	*b++ = (0x00000000);
	*b++ = (_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);

	/* samler state */
#define TEX_COUNT 1
	*b++ = (_3DSTATE_MAP_STATE | (3 * TEX_COUNT));
	*b++ = ((1 << TEX_COUNT) - 1);
	*b = fill_reloc(r++, b-batch, src, I915_GEM_DOMAIN_SAMPLER, 0); b++;
	*b++ = (MAPSURF_32BIT | MT_32BIT_ARGB8888 |
		MS3_TILED_SURFACE |
		(HEIGHT - 1) << MS3_HEIGHT_SHIFT |
		(WIDTH - 1) << MS3_WIDTH_SHIFT);
	*b++ = ((WIDTH-1) << MS4_PITCH_SHIFT);

	*b++ = (_3DSTATE_SAMPLER_STATE | (3 * TEX_COUNT));
	*b++ = ((1 << TEX_COUNT) - 1);
	*b++ = (MIPFILTER_NONE << SS2_MIP_FILTER_SHIFT |
		FILTER_NEAREST << SS2_MAG_FILTER_SHIFT |
		FILTER_NEAREST << SS2_MIN_FILTER_SHIFT);
	*b++ = (TEXCOORDMODE_WRAP << SS3_TCX_ADDR_MODE_SHIFT |
		TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT |
		0 << SS3_TEXTUREMAP_INDEX_SHIFT);
	*b++ = (0x00000000);

	/* render target state */
	*b++ = (_3DSTATE_BUF_INFO_CMD);
	*b++ = (BUF_3D_ID_COLOR_BACK | BUF_3D_TILED_SURFACE |  WIDTH*4);
	*b = fill_reloc(r++, b-batch, dst,
			I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
	b++;

	*b++ = (_3DSTATE_DST_BUF_VARS_CMD);
	*b++ = (COLR_BUF_ARGB8888 |
		DSTORG_HORT_BIAS(0x8) |
		DSTORG_VERT_BIAS(0x8));

	/* draw rect is unconditional */
	*b++ = (_3DSTATE_DRAW_RECT_CMD);
	*b++ = (0x00000000);
	*b++ = (0x00000000);	/* ymin, xmin */
	*b++ = (DRAW_YMAX(HEIGHT - 1) |
		DRAW_XMAX(WIDTH - 1));
	/* yorig, xorig (relate to color buffer?) */
	*b++ = (0x00000000);

	/* texfmt */
	*b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(1) | I1_LOAD_S(2) | I1_LOAD_S(6) | 2);
	*b++ = ((4 << S1_VERTEX_WIDTH_SHIFT) | (4 << S1_VERTEX_PITCH_SHIFT));
	*b++ = (~S2_TEXCOORD_FMT(0, TEXCOORDFMT_NOT_PRESENT) |
		S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D));
	*b++ = (S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE |
		BLENDFUNC_ADD << S6_CBUF_BLEND_FUNC_SHIFT |
		BLENDFACT_ONE << S6_CBUF_SRC_BLEND_FACT_SHIFT |
		BLENDFACT_ZERO << S6_CBUF_DST_BLEND_FACT_SHIFT);

	/* pixel shader */
	*b++ = (_3DSTATE_PIXEL_SHADER_PROGRAM | (1 + 3*3 - 2));
	/* decl FS_T0 */
	*b++ = (D0_DCL |
		REG_TYPE(FS_T0) << D0_TYPE_SHIFT |
		REG_NR(FS_T0) << D0_NR_SHIFT |
		((REG_TYPE(FS_T0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
	*b++ = (0);
	*b++ = (0);
	/* decl FS_S0 */
	*b++ = (D0_DCL |
		(REG_TYPE(FS_S0) << D0_TYPE_SHIFT) |
		(REG_NR(FS_S0) << D0_NR_SHIFT) |
		((REG_TYPE(FS_S0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
	*b++ = (0);
	*b++ = (0);
	/* texld(FS_OC, FS_S0, FS_T0 */
	*b++ = (T0_TEXLD |
		(REG_TYPE(FS_OC) << T0_DEST_TYPE_SHIFT) |
		(REG_NR(FS_OC) << T0_DEST_NR_SHIFT) |
		(REG_NR(FS_S0) << T0_SAMPLER_NR_SHIFT));
	*b++ = ((REG_TYPE(FS_T0) << T1_ADDRESS_REG_TYPE_SHIFT) |
		(REG_NR(FS_T0) << T1_ADDRESS_REG_NR_SHIFT));
	*b++ = (0);

	*b++ = (PRIM3D_RECTLIST | (3*4 - 1));
	*b++ = pack_float(WIDTH);
	*b++ = pack_float(HEIGHT);
	*b++ = pack_float(WIDTH);
	*b++ = pack_float(HEIGHT);

	*b++ = pack_float(0);
	*b++ = pack_float(HEIGHT);
	*b++ = pack_float(0);
	*b++ = pack_float(HEIGHT);

	*b++ = pack_float(0);
	*b++ = pack_float(0);
	*b++ = pack_float(0);
	*b++ = pack_float(0);

	*b++ = MI_BATCH_BUFFER_END;
	if ((b - batch) & 1)
		*b++ = 0;

	assert(b - batch <= 1024);
	handle = gem_create(fd, 4096);
	gem_write(fd, handle, 0, batch, (b-batch)*sizeof(batch[0]));

	assert(r-reloc == 2);

	obj[0].handle = dst;
	obj[0].relocation_count = 0;
	obj[0].relocs_ptr = 0;
	obj[0].alignment = 0;
	obj[0].offset = 0;
	obj[0].flags = 0;
	obj[0].rsvd1 = 0;
	obj[0].rsvd2 = 0;

	obj[1].handle = src;
	obj[1].relocation_count = 0;
	obj[1].relocs_ptr = 0;
	obj[1].alignment = 0;
	obj[1].offset = 0;
	obj[1].flags = 0;
	obj[1].rsvd1 = 0;
	obj[1].rsvd2 = 0;

	obj[2].handle = handle;
	obj[2].relocation_count = 2;
	obj[2].relocs_ptr = (uintptr_t)reloc;
	obj[2].alignment = 0;
	obj[2].offset = 0;
	obj[2].flags = 0;
	obj[2].rsvd1 = obj[2].rsvd2 = 0;

	exec.buffers_ptr = (uintptr_t)obj;
	exec.buffer_count = 3;
	exec.batch_start_offset = 0;
	exec.batch_len = (b-batch)*sizeof(batch[0]);
	exec.DR1 = exec.DR4 = 0;
	exec.num_cliprects = 0;
	exec.cliprects_ptr = 0;
	exec.flags = 0;
	i915_execbuffer2_set_context_id(exec, 0);
	exec.rsvd2 = 0;

	ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
	while (ret && errno == EBUSY) {
		drmCommandNone(fd, DRM_I915_GEM_THROTTLE);
		ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
	}
	assert(ret == 0);

	gem_close(fd, handle);
}
示例#3
0
文件: i830_state.c 项目: nikai3d/mesa
static void
i830_init_packets(struct i830_context *i830)
{
   /* Zero all state */
   memset(&i830->state, 0, sizeof(i830->state));

   /* Set default blend state */
   i830->state.TexBlend[0][0] = (_3DSTATE_MAP_BLEND_OP_CMD(0) |
                                 TEXPIPE_COLOR |
                                 ENABLE_TEXOUTPUT_WRT_SEL |
                                 TEXOP_OUTPUT_CURRENT |
                                 DISABLE_TEX_CNTRL_STAGE |
                                 TEXOP_SCALE_1X |
                                 TEXOP_MODIFY_PARMS |
                                 TEXOP_LAST_STAGE | TEXBLENDOP_ARG1);
   i830->state.TexBlend[0][1] = (_3DSTATE_MAP_BLEND_OP_CMD(0) |
                                 TEXPIPE_ALPHA |
                                 ENABLE_TEXOUTPUT_WRT_SEL |
                                 TEXOP_OUTPUT_CURRENT |
                                 TEXOP_SCALE_1X |
                                 TEXOP_MODIFY_PARMS | TEXBLENDOP_ARG1);
   i830->state.TexBlend[0][2] = (_3DSTATE_MAP_BLEND_ARG_CMD(0) |
                                 TEXPIPE_COLOR |
                                 TEXBLEND_ARG1 |
                                 TEXBLENDARG_MODIFY_PARMS |
                                 TEXBLENDARG_DIFFUSE);
   i830->state.TexBlend[0][3] = (_3DSTATE_MAP_BLEND_ARG_CMD(0) |
                                 TEXPIPE_ALPHA |
                                 TEXBLEND_ARG1 |
                                 TEXBLENDARG_MODIFY_PARMS |
                                 TEXBLENDARG_DIFFUSE);

   i830->state.TexBlendWordsUsed[0] = 4;


   i830->state.Ctx[I830_CTXREG_VF] = 0;
   i830->state.Ctx[I830_CTXREG_VF2] = 0;

   i830->state.Ctx[I830_CTXREG_AA] = (_3DSTATE_AA_CMD |
                                      AA_LINE_ECAAR_WIDTH_ENABLE |
                                      AA_LINE_ECAAR_WIDTH_1_0 |
                                      AA_LINE_REGION_WIDTH_ENABLE |
                                      AA_LINE_REGION_WIDTH_1_0 |
                                      AA_LINE_DISABLE);

   i830->state.Ctx[I830_CTXREG_ENABLES_1] = (_3DSTATE_ENABLES_1_CMD |
                                             DISABLE_LOGIC_OP |
                                             DISABLE_STENCIL_TEST |
                                             DISABLE_DEPTH_BIAS |
                                             DISABLE_SPEC_ADD |
                                             DISABLE_FOG |
                                             DISABLE_ALPHA_TEST |
                                             DISABLE_COLOR_BLEND |
                                             DISABLE_DEPTH_TEST);

#if 000                         /* XXX all the stencil enable state is set in i830Enable(), right? */
   if (i830->intel.hw_stencil) {
      i830->state.Ctx[I830_CTXREG_ENABLES_2] = (_3DSTATE_ENABLES_2_CMD |
                                                ENABLE_STENCIL_WRITE |
                                                ENABLE_TEX_CACHE |
                                                ENABLE_DITHER |
                                                ENABLE_COLOR_MASK |
                                                /* set no color comps disabled */
                                                ENABLE_COLOR_WRITE |
                                                ENABLE_DEPTH_WRITE);
   }
   else
#endif
   {
      i830->state.Ctx[I830_CTXREG_ENABLES_2] = (_3DSTATE_ENABLES_2_CMD |
                                                DISABLE_STENCIL_WRITE |
                                                ENABLE_TEX_CACHE |
                                                ENABLE_DITHER |
                                                ENABLE_COLOR_MASK |
                                                /* set no color comps disabled */
                                                ENABLE_COLOR_WRITE |
                                                ENABLE_DEPTH_WRITE);
   }

   i830->state.Ctx[I830_CTXREG_STATE1] = (_3DSTATE_MODES_1_CMD |
                                          ENABLE_COLR_BLND_FUNC |
                                          BLENDFUNC_ADD |
                                          ENABLE_SRC_BLND_FACTOR |
                                          SRC_BLND_FACT(BLENDFACT_ONE) |
                                          ENABLE_DST_BLND_FACTOR |
                                          DST_BLND_FACT(BLENDFACT_ZERO));

   i830->state.Ctx[I830_CTXREG_STATE2] = (_3DSTATE_MODES_2_CMD |
                                          ENABLE_GLOBAL_DEPTH_BIAS |
                                          GLOBAL_DEPTH_BIAS(0) |
                                          ENABLE_ALPHA_TEST_FUNC |
                                          ALPHA_TEST_FUNC(COMPAREFUNC_ALWAYS)
                                          | ALPHA_REF_VALUE(0));

   i830->state.Ctx[I830_CTXREG_STATE3] = (_3DSTATE_MODES_3_CMD |
                                          ENABLE_DEPTH_TEST_FUNC |
                                          DEPTH_TEST_FUNC(COMPAREFUNC_LESS) |
                                          ENABLE_ALPHA_SHADE_MODE |
                                          ALPHA_SHADE_MODE(SHADE_MODE_LINEAR)
                                          | ENABLE_FOG_SHADE_MODE |
                                          FOG_SHADE_MODE(SHADE_MODE_LINEAR) |
                                          ENABLE_SPEC_SHADE_MODE |
                                          SPEC_SHADE_MODE(SHADE_MODE_LINEAR) |
                                          ENABLE_COLOR_SHADE_MODE |
                                          COLOR_SHADE_MODE(SHADE_MODE_LINEAR)
                                          | ENABLE_CULL_MODE | CULLMODE_NONE);

   i830->state.Ctx[I830_CTXREG_STATE4] = (_3DSTATE_MODES_4_CMD |
                                          ENABLE_LOGIC_OP_FUNC |
                                          LOGIC_OP_FUNC(LOGICOP_COPY) |
                                          ENABLE_STENCIL_TEST_MASK |
                                          STENCIL_TEST_MASK(0xff) |
                                          ENABLE_STENCIL_WRITE_MASK |
                                          STENCIL_WRITE_MASK(0xff));

   i830->state.Ctx[I830_CTXREG_STENCILTST] = (_3DSTATE_STENCIL_TEST_CMD |
                                              ENABLE_STENCIL_PARMS |
                                              STENCIL_FAIL_OP(STENCILOP_KEEP)
                                              |
                                              STENCIL_PASS_DEPTH_FAIL_OP
                                              (STENCILOP_KEEP) |
                                              STENCIL_PASS_DEPTH_PASS_OP
                                              (STENCILOP_KEEP) |
                                              ENABLE_STENCIL_TEST_FUNC |
                                              STENCIL_TEST_FUNC
                                              (COMPAREFUNC_ALWAYS) |
                                              ENABLE_STENCIL_REF_VALUE |
                                              STENCIL_REF_VALUE(0));

   i830->state.Ctx[I830_CTXREG_STATE5] = (_3DSTATE_MODES_5_CMD | FLUSH_TEXTURE_CACHE | ENABLE_SPRITE_POINT_TEX | SPRITE_POINT_TEX_OFF | ENABLE_FIXED_LINE_WIDTH | FIXED_LINE_WIDTH(0x2) |       /* 1.0 */
                                          ENABLE_FIXED_POINT_WIDTH |
                                          FIXED_POINT_WIDTH(1));

   i830->state.Ctx[I830_CTXREG_IALPHAB] = (_3DSTATE_INDPT_ALPHA_BLEND_CMD |
                                           DISABLE_INDPT_ALPHA_BLEND |
                                           ENABLE_ALPHA_BLENDFUNC |
                                           ABLENDFUNC_ADD);

   i830->state.Ctx[I830_CTXREG_FOGCOLOR] = (_3DSTATE_FOG_COLOR_CMD |
                                            FOG_COLOR_RED(0) |
                                            FOG_COLOR_GREEN(0) |
                                            FOG_COLOR_BLUE(0));

   i830->state.Ctx[I830_CTXREG_BLENDCOLOR0] = _3DSTATE_CONST_BLEND_COLOR_CMD;
   i830->state.Ctx[I830_CTXREG_BLENDCOLOR1] = 0;

   i830->state.Ctx[I830_CTXREG_MCSB0] = _3DSTATE_MAP_COORD_SETBIND_CMD;
   i830->state.Ctx[I830_CTXREG_MCSB1] = (TEXBIND_SET3(TEXCOORDSRC_VTXSET_3) |
                                         TEXBIND_SET2(TEXCOORDSRC_VTXSET_2) |
                                         TEXBIND_SET1(TEXCOORDSRC_VTXSET_1) |
                                         TEXBIND_SET0(TEXCOORDSRC_VTXSET_0));

   i830->state.RasterRules[I830_RASTER_RULES] = (_3DSTATE_RASTER_RULES_CMD |
						 ENABLE_POINT_RASTER_RULE |
						 OGL_POINT_RASTER_RULE |
						 ENABLE_LINE_STRIP_PROVOKE_VRTX |
						 ENABLE_TRI_FAN_PROVOKE_VRTX |
						 ENABLE_TRI_STRIP_PROVOKE_VRTX |
						 LINE_STRIP_PROVOKE_VRTX(1) |
						 TRI_FAN_PROVOKE_VRTX(2) |
						 TRI_STRIP_PROVOKE_VRTX(2));


   i830->state.Stipple[I830_STPREG_ST0] = _3DSTATE_STIPPLE;

   i830->state.Buffer[I830_DESTREG_DV0] = _3DSTATE_DST_BUF_VARS_CMD;
   i830->state.Buffer[I830_DESTREG_SENABLE] = (_3DSTATE_SCISSOR_ENABLE_CMD |
                                               DISABLE_SCISSOR_RECT);
   i830->state.Buffer[I830_DESTREG_SR0] = _3DSTATE_SCISSOR_RECT_0_CMD;
   i830->state.Buffer[I830_DESTREG_SR1] = 0;
   i830->state.Buffer[I830_DESTREG_SR2] = 0;
}
示例#4
0
   _3DSTATE_COORD_SET_BINDINGS |
             CSB_TCB(0, 0) |
             CSB_TCB(1, 1) |
             CSB_TCB(2, 2) |
             CSB_TCB(3, 3) |
             CSB_TCB(4, 4) |
             CSB_TCB(5, 5) |
             CSB_TCB(6, 6) |
             CSB_TCB(7, 7),

   _3DSTATE_RASTER_RULES_CMD |
             ENABLE_POINT_RASTER_RULE |
             OGL_POINT_RASTER_RULE |
             ENABLE_LINE_STRIP_PROVOKE_VRTX |
             ENABLE_TRI_FAN_PROVOKE_VRTX |
             LINE_STRIP_PROVOKE_VRTX(1) |
             TRI_FAN_PROVOKE_VRTX(2) |
             ENABLE_TEXKILL_3D_4D |
             TEXKILL_4D,

   _3DSTATE_DEPTH_SUBRECT_DISABLE,

   /* disable indirect state for now
    */
   _3DSTATE_LOAD_INDIRECT | 0, 0};

static void
emit_invariant(struct i915_context *i915)
{
   i915_winsys_batchbuffer_write(i915->batch, invariant_state,
                                 Elements(invariant_state)*sizeof(uint32_t));
示例#5
0
void I915EmitInvarientState(ScrnInfoPtr scrn)
{
	intel_screen_private *intel = intel_get_screen_private(scrn);

	assert(intel->in_batch_atomic);

	OUT_BATCH(_3DSTATE_AA_CMD |
		  AA_LINE_ECAAR_WIDTH_ENABLE |
		  AA_LINE_ECAAR_WIDTH_1_0 |
		  AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);

	/* Disable independent alpha blend */
	OUT_BATCH(_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
		  IAB_MODIFY_ENABLE |
		  IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
		  IAB_MODIFY_SRC_FACTOR | (BLENDFACT_ONE <<
					   IAB_SRC_FACTOR_SHIFT) |
		  IAB_MODIFY_DST_FACTOR | (BLENDFACT_ZERO <<
					   IAB_DST_FACTOR_SHIFT));

	OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
	OUT_BATCH(0);

	OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
	OUT_BATCH(0);

	OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
	OUT_BATCH(0);

	/* Don't support texture crossbar yet */
	OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
		  CSB_TCB(0, 0) |
		  CSB_TCB(1, 1) |
		  CSB_TCB(2, 2) |
		  CSB_TCB(3, 3) |
		  CSB_TCB(4, 4) |
		  CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));

	OUT_BATCH(_3DSTATE_RASTER_RULES_CMD |
		  ENABLE_POINT_RASTER_RULE |
		  OGL_POINT_RASTER_RULE |
		  ENABLE_LINE_STRIP_PROVOKE_VRTX |
		  ENABLE_TRI_FAN_PROVOKE_VRTX |
		  LINE_STRIP_PROVOKE_VRTX(1) |
		  TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D);

	OUT_BATCH(_3DSTATE_MODES_4_CMD |
		  ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
		  ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
		  ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));

	OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | I1_LOAD_S(4) | I1_LOAD_S(5) | 2);
	OUT_BATCH(0x00000000);	/* Disable texture coordinate wrap-shortest */
	OUT_BATCH((1 << S4_POINT_WIDTH_SHIFT) |
		  S4_LINE_WIDTH_ONE |
		  S4_CULLMODE_NONE |
		  S4_VFMT_XY);
	OUT_BATCH(0x00000000);	/* Stencil. */

	OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
	OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
	OUT_BATCH(0);
	OUT_BATCH(0);

	OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);

	OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0);	/* disable indirect state */
	OUT_BATCH(0);

	OUT_BATCH(_3DSTATE_STIPPLE);
	OUT_BATCH(0x00000000);

	OUT_BATCH(_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
}
static void
i915_emit_invarient_state(struct intel_context *intel)
{
   BATCH_LOCALS;

   BEGIN_BATCH(200, IGNORE_CLIPRECTS);

   OUT_BATCH(_3DSTATE_AA_CMD |
             AA_LINE_ECAAR_WIDTH_ENABLE |
             AA_LINE_ECAAR_WIDTH_1_0 |
             AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);

   OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
   OUT_BATCH(0);

   OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
   OUT_BATCH(0);

   OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
   OUT_BATCH(0);

   /* Don't support texture crossbar yet */
   OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
             CSB_TCB(0, 0) |
             CSB_TCB(1, 1) |
             CSB_TCB(2, 2) |
             CSB_TCB(3, 3) |
             CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));

   OUT_BATCH(_3DSTATE_RASTER_RULES_CMD |
             ENABLE_POINT_RASTER_RULE |
             OGL_POINT_RASTER_RULE |
             ENABLE_LINE_STRIP_PROVOKE_VRTX |
             ENABLE_TRI_FAN_PROVOKE_VRTX |
             LINE_STRIP_PROVOKE_VRTX(1) |
             TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D);

   /* Need to initialize this to zero.
    */
   OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0));
   OUT_BATCH(0);

   /* XXX: Use this */
   OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);

   OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
   OUT_BATCH(0);
   OUT_BATCH(0);

   OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);

   OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0);       /* disable indirect state */
   OUT_BATCH(0);


   /* Don't support twosided stencil yet */
   OUT_BATCH(_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
   OUT_BATCH(0);

   ADVANCE_BATCH();
}