static int iwdg_stm32_init(struct device *dev)
{
#ifdef CONFIG_IWDG_STM32_START_AT_BOOT
IWDG_TypeDef *iwdg = IWDG_STM32_STRUCT(dev);
struct wdt_timeout_cfg config = {
.window.max = CONFIG_IWDG_STM32_TIMEOUT * USEC_PER_MSEC,
};
LL_IWDG_Enable(iwdg);
iwdg_stm32_install_timeout(dev, &config);
#endif
/*
* The ST production value for the option bytes where WDG_SW bit is
* present is 0x00FF55AA, namely the Software watchdog mode is
* enabled by default.
* If the IWDG is started by either hardware option or software access,
* the LSI oscillator is forced ON and cannot be disabled.
*
* t_IWDG(ms) = t_LSI(ms) x 4 x 2^(IWDG_PR[2:0]) x (IWDG_RLR[11:0] + 1)
*/
return 0;
}
static struct iwdg_stm32_data iwdg_stm32_dev_data = {
.Instance = (IWDG_TypeDef *)DT_ST_STM32_WATCHDOG_0_BASE_ADDRESS
};
DEVICE_AND_API_INIT(iwdg_stm32, DT_ST_STM32_WATCHDOG_0_LABEL,
iwdg_stm32_init, &iwdg_stm32_dev_data, NULL,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&iwdg_stm32_api);
void
watchdog_init(void)
{
LL_IWDG_EnableWriteAccess(IWDG);
/* IWDG timer is 40 KHz, configure to trigger every seconds */
LL_IWDG_SetPrescaler(IWDG, LL_IWDG_PRESCALER_16);
LL_IWDG_SetReloadCounter(IWDG, 2500);
LL_IWDG_Enable(IWDG);
}
static int iwdg_stm32_setup(struct device *dev, u8_t options)
{
IWDG_TypeDef *iwdg = IWDG_STM32_STRUCT(dev);
/* Deactivate running when debugger is attached. */
if (options & WDT_OPT_PAUSE_HALTED_BY_DBG) {
#if defined(CONFIG_SOC_SERIES_STM32F0X)
LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_DBGMCU);
#elif defined(CONFIG_SOC_SERIES_STM32L0X)
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_DBGMCU);
#endif
LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP);
}
if (options & WDT_OPT_PAUSE_IN_SLEEP) {
return -ENOTSUP;
}
LL_IWDG_Enable(iwdg);
return 0;
}
