/**
* @brief Return PLLI2S clock frequency used for SPDIFRX domain
* @retval PLLI2S clock frequency (in Hz)
*/
uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void)
{
uint32_t pllinputfreq = 0U, pllsource = 0U;
/* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN
SPDIFRX Domain clock = PLLI2S_VCO / PLLI2SP
*/
pllsource = LL_RCC_PLL_GetMainSource();
switch (pllsource)
{
case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
pllinputfreq = HSI_VALUE;
break;
case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
pllinputfreq = HSE_VALUE;
break;
default:
pllinputfreq = HSI_VALUE;
break;
}
return __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetP());
}
/**
* @brief Return PLL clock frequency used for system domain
* @retval PLL clock frequency (in Hz)
*/
uint32_t RCC_PLL_GetFreqDomain_SYS(void)
{
uint32_t pllinputfreq = 0U, pllsource = 0U;
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */
/* Get PLL source */
pllsource = LL_RCC_PLL_GetMainSource();
switch (pllsource)
{
case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
pllinputfreq = HSI_VALUE;
break;
case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllinputfreq = HSE_VALUE;
break;
default:
pllinputfreq = HSI_VALUE;
break;
}
return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetDivider());
}
/**
* @brief Return PLLI2S clock frequency used for SAI1 and SAI2 domains
* @retval PLLI2S clock frequency (in Hz)
*/
uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void)
{
uint32_t pllinputfreq = 0U, pllsource = 0U;
/* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN
SAI1 and SAI2 domains clock = (PLLI2S_VCO / PLLI2SQ) / PLLI2SDIVQ
*/
pllsource = LL_RCC_PLL_GetMainSource();
switch (pllsource)
{
case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
pllinputfreq = HSI_VALUE;
break;
case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
pllinputfreq = HSE_VALUE;
break;
default:
pllinputfreq = HSI_VALUE;
break;
}
return __LL_RCC_CALC_PLLI2S_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ(), LL_RCC_PLLI2S_GetDIVQ());
}
/**
* @brief Return PLLSAI clock frequency used for LTDC domain
* @retval PLLSAI clock frequency (in Hz)
*/
uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void)
{
uint32_t pllinputfreq = 0U, pllsource = 0U;
/* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN
LTDC Domain clock = (PLLSAI_VCO / PLLSAIR) / PLLSAIDIVR
*/
pllsource = LL_RCC_PLL_GetMainSource();
switch (pllsource)
{
case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
pllinputfreq = HSI_VALUE;
break;
case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
pllinputfreq = HSE_VALUE;
break;
default:
pllinputfreq = HSI_VALUE;
break;
}
return __LL_RCC_CALC_PLLSAI_LTDC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetR(), LL_RCC_PLLSAI_GetDIVR());
}
/**
* @brief Return PLL clock frequency used for 48 MHz domain
* @retval PLL clock frequency (in Hz)
*/
uint32_t RCC_PLL_GetFreqDomain_48M(void)
{
uint32_t pllinputfreq = 0U, pllsource = 0U;
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
48M Domain clock = PLL_VCO / PLLQ
*/
pllsource = LL_RCC_PLL_GetMainSource();
switch (pllsource)
{
case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
pllinputfreq = HSI_VALUE;
break;
case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllinputfreq = HSE_VALUE;
break;
default:
pllinputfreq = HSI_VALUE;
break;
}
return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
}
static int i2s_stm32_set_clock(struct device *dev, u32_t bit_clk_freq)
{
const struct i2s_stm32_cfg *cfg = DEV_CFG(dev);
u32_t pll_src = LL_RCC_PLL_GetMainSource();
int freq_in;
u8_t i2s_div, i2s_odd;
freq_in = (pll_src == LL_RCC_PLLSOURCE_HSI) ?
HSI_VALUE : CONFIG_CLOCK_STM32_HSE_CLOCK;
#ifdef CONFIG_I2S_STM32_USE_PLLI2S_ENABLE
/* Set PLLI2S */
LL_RCC_PLLI2S_Disable();
LL_RCC_PLLI2S_ConfigDomain_I2S(pll_src,
CONFIG_I2S_STM32_PLLI2S_PLLM,
CONFIG_I2S_STM32_PLLI2S_PLLN,
pllr(CONFIG_I2S_STM32_PLLI2S_PLLR));
LL_RCC_PLLI2S_Enable();
/* wait until PLLI2S gets locked */
while (!LL_RCC_PLLI2S_IsReady()) {
if (plli2s_ms_count++ > PLLI2S_MAX_MS_TIME) {
return -EIO;
}
/* wait 1 ms */
k_sleep(1);
}
LOG_DBG("PLLI2S is locked");
/* Adjust freq_in according to PLLM, PLLN, PLLR */
float freq_tmp;
freq_tmp = freq_in / CONFIG_I2S_STM32_PLLI2S_PLLM;
freq_tmp *= CONFIG_I2S_STM32_PLLI2S_PLLN;
freq_tmp /= CONFIG_I2S_STM32_PLLI2S_PLLR;
freq_in = (int) freq_tmp;
#endif /* CONFIG_I2S_STM32_USE_PLLI2S_ENABLE */
/* Select clock source */
LL_RCC_SetI2SClockSource(cfg->i2s_clk_sel);
/*
* The ratio between input clock (I2SxClk) and output
* clock on the pad (I2S_CK) is obtained using the
* following formula:
* (i2s_div * 2) + i2s_odd
*/
i2s_div = div_round_closest(freq_in, bit_clk_freq);
i2s_odd = (i2s_div & 0x1) ? 1 : 0;
i2s_div >>= 1;
LOG_DBG("i2s_div: %d - i2s_odd: %d", i2s_div, i2s_odd);
LL_I2S_SetPrescalerLinear(cfg->i2s, i2s_div);
LL_I2S_SetPrescalerParity(cfg->i2s, i2s_odd);
return 0;
}
/**
* @brief Return PLL clock frequency used for system domain
* @retval PLL clock frequency (in Hz)
*/
uint32_t RCC_PLL_GetFreqDomain_SYS(void)
{
uint32_t pllinputfreq = 0U, pllsource = 0U;
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */
/* Get PLL source */
pllsource = LL_RCC_PLL_GetMainSource();
switch (pllsource)
{
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
pllinputfreq = HSI_VALUE;
#else
case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */
pllinputfreq = HSI_VALUE / 2;
#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
break;
#if defined(RCC_CFGR_SW_HSI48)
case LL_RCC_PLLSOURCE_HSI48: /* HSI48 used as PLL clock source */
pllinputfreq = HSI48_VALUE;
break;
#endif /* RCC_CFGR_SW_HSI48 */
case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllinputfreq = HSE_VALUE;
break;
default:
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
pllinputfreq = HSI_VALUE;
#else
pllinputfreq = HSI_VALUE / 2;
#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
break;
}
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetPrediv());
#else
return __LL_RCC_CALC_PLLCLK_FREQ((pllinputfreq / (LL_RCC_PLL_GetPrediv() + 1U)), LL_RCC_PLL_GetMultiplicator());
#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
}
/**
* @brief Return PLLSAI2 clock frequency used for ADC domain
* @retval PLLSAI2 clock frequency (in Hz)
*/
uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void)
{
uint32_t pllinputfreq = 0, pllsource = 0;
/* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI2N
48M Domain clock = PLLSAI2_VCO / PLLSAI2R
*/
pllsource = LL_RCC_PLL_GetMainSource();
switch (pllsource)
{
case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */
pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
(LL_RCC_MSI_IsEnabledRangeSelect() ?
LL_RCC_MSI_GetRange() :
LL_RCC_MSI_GetRangeAfterStandby()));
break;
case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */
pllinputfreq = HSI_VALUE;
break;
case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */
pllinputfreq = HSE_VALUE;
break;
default:
pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
(LL_RCC_MSI_IsEnabledRangeSelect() ?
LL_RCC_MSI_GetRange() :
LL_RCC_MSI_GetRangeAfterStandby()));
break;
}
return __LL_RCC_CALC_PLLSAI2_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR());
}
/**
* @brief Return SAIx clock frequency
* @param SAIxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_SAI1_CLKSOURCE
* @arg @ref LL_RCC_SAI2_CLKSOURCE
* @retval SAI clock frequency (in Hz)
* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
* - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
*/
uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
{
uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
/* Check parameter */
assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
if (SAIxSource == LL_RCC_SAI1_CLKSOURCE)
{
/* SAI1CLK clock frequency */
switch (LL_RCC_GetSAIClockSource(SAIxSource))
{
case LL_RCC_SAI1_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 clock source */
if (LL_RCC_PLLSAI_IsReady())
{
sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
}
break;
case LL_RCC_SAI1_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 clock source */
if (LL_RCC_PLLI2S_IsReady())
{
sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
}
break;
#if defined(RCC_SAI1SEL_PLLSRC_SUPPORT)
case LL_RCC_SAI1_CLKSOURCE_PLLSRC:
switch (LL_RCC_PLL_GetMainSource())
{
case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI1 clock source */
if (LL_RCC_HSE_IsReady())
{
sai_frequency = HSE_VALUE;
}
break;
case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI1 clock source */
default:
if (LL_RCC_HSI_IsReady())
{
sai_frequency = HSI_VALUE;
}
break;
}
break;
#endif /* RCC_SAI1SEL_PLLSRC_SUPPORT */
case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */
default:
sai_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
break;
}
}
else
{
if (SAIxSource == LL_RCC_SAI2_CLKSOURCE)
{
/* SAI2CLK clock frequency */
switch (LL_RCC_GetSAIClockSource(SAIxSource))
{
case LL_RCC_SAI2_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI2 clock source */
if (LL_RCC_PLLSAI_IsReady())
{
sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
}
break;
case LL_RCC_SAI2_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI2 clock source */
if (LL_RCC_PLLI2S_IsReady())
{
sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
}
break;
#if defined(RCC_SAI2SEL_PLLSRC_SUPPORT)
case LL_RCC_SAI2_CLKSOURCE_PLLSRC:
switch (LL_RCC_PLL_GetMainSource())
{
case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI2 clock source */
if (LL_RCC_HSE_IsReady())
{
sai_frequency = HSE_VALUE;
}
break;
case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI2 clock source */
default:
if (LL_RCC_HSI_IsReady())
{
sai_frequency = HSI_VALUE;
}
break;
}
break;
#endif /* RCC_SAI2SEL_PLLSRC_SUPPORT */
case LL_RCC_SAI2_CLKSOURCE_PIN: /* External input clock used as SAI2 clock source */
default:
sai_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
break;
}
}
}
return sai_frequency;
}
