static void select_socket(UINT8 socket_id)
{
AMD_CONFIG_PARAMS StdHeader;
UINT32 PciData32;
UINT8 PciData8;
PCI_ADDR PciAddress;
/* Set SMBus MMIO. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0x90);
PciData32 = (SMBUS0_BASE_ADDRESS & 0xFFFFFFF0) | BIT0;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData32, &StdHeader);
/* Enable SMBus MMIO. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2);
LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ;
PciData8 |= BIT0;
LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader);
switch (socket_id) {
case 0:
/* Switch onto the First CPU Socket SMBus */
writeSmbusByte(SMBUS0_BASE_ADDRESS, LTC4305_SMBUS_ADDR, 0x80, 0x03);
break;
case 1:
/* Switch onto the Second CPU Socket SMBus */
writeSmbusByte(SMBUS0_BASE_ADDRESS, LTC4305_SMBUS_ADDR, 0x40, 0x03);
break;
default:
/* Switch off two CPU Sockets SMBus */
writeSmbusByte(SMBUS0_BASE_ADDRESS, LTC4305_SMBUS_ADDR, 0x00, 0x03);
break;
}
}
/**
* Workaround for Erratum #687 for TN processors.
*
* AGESA should program F5x88[14] with the fused value from F3x1FC[29] and
* program F2x408[CpuElevPrioDis] with inversed fuse value from F3x1FC[29] for all TN parts.
*
* @param[in] Data The table data value, for example to indicate which CPU and Platform types matched.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
Erratum687Workaround (
IN UINT32 Data,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
PRODUCT_INFO_REGISTER ProductInfo;
NB_CFG_4_REGISTER NbCfg4;
GMC_TO_DCT_CTL_2_REGISTER GmcToDctCtrl2;
UINT32 DctSelCnt;
DCT_CFG_SEL_REGISTER DctCfgSel;
PciAddress.AddressValue = PRCT_INFO_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&ProductInfo, StdHeader);
PciAddress.AddressValue = NB_CFG_REG4_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader);
NbCfg4.Bit14 = ProductInfo.EnDcqChgPriToHigh;
LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader);
for (DctSelCnt = 0; DctSelCnt <= 1; DctSelCnt++) {
PciAddress.AddressValue = GMC_TO_DCT_CTL_2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&GmcToDctCtrl2, StdHeader);
GmcToDctCtrl2.CpuElevPrioDis = ~ProductInfo.EnDcqChgPriToHigh;
LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&GmcToDctCtrl2, StdHeader);
PciAddress.AddressValue = DCT_CFG_SEL_REG_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&DctCfgSel, StdHeader);
DctCfgSel.DctCfgSel = ~DctCfgSel.DctCfgSel;
LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&DctCfgSel, StdHeader);
}
}
STATIC
VOID
SetupFch (
IN UINT16
IN IoBase
)
{
AMD_CONFIG_PARAMS StdHeader;
UINT32 PciData32;
UINT8 PciData8;
PCI_ADDR PciAddress;
/* Set SMBUS MMIO. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0x90);
PciData32 = (SMBUS_BASE_ADDR & 0xFFFFFFF0) | BIT0;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData32, &StdHeader);
/* Enable SMBUS MMIO. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2);
LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ;
PciData8 |= BIT0;
LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader);
/* set SMBus clock to 400 KHz */
__outbyte (IoBase + 0x0E, 66000000 / 400000 / 4);
}
/**
* Set the Processor Name String register based on F5x194/198
*
* This function copies F5x198_x[B:0] to MSR_C001_00[35:30]
*
* @param[in] FamilyServices The current Family Specific Services.
* @param[in] EarlyParams Service parameters.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F15SetBrandIdRegistersAtEarly (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 PciData;
UINT32 ExceptionId;
UINT32 MsrIndex;
UINT64 MsrData;
UINT64 *MsrNameStringPtrPtr;
PCI_ADDR PciAddress;
if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) {
if (IsException (&ExceptionId, StdHeader)) {
ASSERT (ExceptionId < (sizeof (CpuF15ExceptionBrandIdString) / sizeof (CpuF15ExceptionBrandIdString[0])));
MsrNameStringPtrPtr = (UINT64 *) CpuF15ExceptionBrandIdString[ExceptionId].Stringstart;
} else {
OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
PciAddress.Address.Function = FUNC_5;
PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT;
// check if D18F5x198_x0 is 00000000h.
PciData = 0;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
PciAddress.Address.Register = NAME_STRING_DATA_PORT;
LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
if (PciData != 0) {
for (MsrIndex = 0; MsrIndex <= (MSR_CPUID_NAME_STRING5 - MSR_CPUID_NAME_STRING0); MsrIndex++) {
PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT;
PciData = MsrIndex * 2;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
PciAddress.Address.Register = NAME_STRING_DATA_PORT;
LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
((PROCESSOR_NAME_STRING *) (&MsrData))->lo = PciData;
PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT;
PciData = (MsrIndex * 2) + 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
PciAddress.Address.Register = NAME_STRING_DATA_PORT;
LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
((PROCESSOR_NAME_STRING *) (&MsrData))->hi = PciData;
LibAmdMsrWrite ((MsrIndex + MSR_CPUID_NAME_STRING0), &MsrData, StdHeader);
}
return;
} else {
// It is unprogrammed (unfused) parts and use a name string of "AMD Unprogrammed Engineering Sample"
MsrNameStringPtrPtr = (UINT64 *) str_Unprogrammed_Sample;
}
}
// Put values into name MSRs, Always write the full 48 bytes
for (MsrIndex = MSR_CPUID_NAME_STRING0; MsrIndex <= MSR_CPUID_NAME_STRING5; MsrIndex++) {
LibAmdMsrWrite (MsrIndex, MsrNameStringPtrPtr, StdHeader);
MsrNameStringPtrPtr++;
}
}
}
/**
* Family 14h model 0 - 0xF core 0 entry point for programming registers for lower
* power consumption.
*
* Set up D18F6x94[CpuPstateThrEn, CpuPstateThr], and D18F4x134[IntRateCC6DecrRate
* according to the BKDG.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParams Service parameters
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F14OptimizeForLowPowerInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 NumBoostStates;
UINT32 LocalPciRegister;
BOOLEAN OptimizeForLowPower;
BOOLEAN IsRevC;
PCI_ADDR PciAddress;
CPU_LOGICAL_ID CpuFamilyRevision;
PciAddress.AddressValue = PRODUCT_INFO_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if ((((PRODUCT_INFO_REGISTER *) &LocalPciRegister)->LowPowerDefault == 1) &&
(CpuEarlyParams->PlatformConfig.PlatformProfile.PlatformPowerPolicy == BatteryLife)) {
OptimizeForLowPower = TRUE;
} else {
OptimizeForLowPower = FALSE;
}
// Get F4x15C [4:2] NumBoostStates
// Get IsRevC
NumBoostStates = 0;
IsRevC = FALSE;
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
if ((CpuFamilyRevision.Revision & AMD_F14_ON_Cx) != 0) {
IsRevC = TRUE;
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
NumBoostStates = (UINT8) ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates;
}
// F6x94[2:0] CpuPstateThr
PciAddress.AddressValue = NB_PSTATE_CFG_HIGH_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (OptimizeForLowPower) {
((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 0;
} else {
if (NumBoostStates == 0) {
((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 1;
} else {
((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 2;
}
}
// F6x94[3] CpuPstateThrEn = 1
((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThrEn = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
// F4x134[31:27] IntRateCC6DecrRate
PciAddress.AddressValue = CSTATE_MON_CTRL3_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((CSTATE_MON_CTRL3_REGISTER *) &LocalPciRegister)->IntRateCC6DecrRate = (OptimizeForLowPower || IsRevC) ? 0x18 : 0x8;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
/**
* Main entry point for initializing the Thermal Control
* safety net feature.
*
* This must be run by all Family 16h Kabini core 0s in the system.
*
* @param[in] HtcServices The current CPU's family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F16KbInitializeHtc (
IN HTC_FAMILY_SERVICES *HtcServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 HtcTempLimit;
NB_CAPS_REGISTER NbCaps;
HTC_REGISTER HtcReg;
CLK_PWR_TIMING_CTRL2_REGISTER Cptc2;
POPUP_PSTATE_REGISTER PopUpPstate;
PCI_ADDR PciAddress;
UINT32 D0F0xBC_xC0107097;
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader);
if (NbCaps.HtcCapable == 1) {
// Enable HTC
PciAddress.Address.Register = HTC_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &HtcReg, StdHeader);
GnbRegisterReadKB (GnbGetHandle (StdHeader), 0x4, 0xC0107097, &D0F0xBC_xC0107097, 0, StdHeader);
HtcReg.HtcTmpLmt = (D0F0xBC_xC0107097 >> 3) & 0x7F;
if (HtcReg.HtcTmpLmt != 0) {
// Enable HTC
HtcReg.HtcEn = 1;
PciAddress.Address.Register = CPTC2_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2, StdHeader);
if (HtcReg.HtcPstateLimit > Cptc2.HwPstateMaxVal) {
// F3xDC[HwPstateMaxVal] = F3x64[HtcPstateLimit]
Cptc2.HwPstateMaxVal = HtcReg.HtcPstateLimit;
LibAmdPciWrite (AccessWidth32, PciAddress, &Cptc2, StdHeader);
// F3xA8[PopDownPstate] = F3xDC[HwPstateMaxVal]
PciAddress.Address.Register = POPUP_PSTATE_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &PopUpPstate, StdHeader);
PopUpPstate.PopDownPstate = Cptc2.HwPstateMaxVal;
LibAmdPciWrite (AccessWidth32, PciAddress, &PopUpPstate, StdHeader);
}
if ((PlatformConfig->HtcTemperatureLimit >= 520) && (PlatformConfig->LhtcTemperatureLimit != 0)) {
HtcTempLimit = ((PlatformConfig->HtcTemperatureLimit - 520) / 5);
if (HtcTempLimit < HtcReg.HtcTmpLmt) {
HtcReg.HtcTmpLmt = HtcTempLimit;
}
}
} else {
// Disable HTC
HtcReg.HtcEn = 0;
}
PciAddress.Address.Register = HTC_REG;
IDS_OPTION_HOOK (IDS_HTC_CTRL, &HtcReg, StdHeader);
LibAmdPciWrite (AccessWidth32, PciAddress, &HtcReg, StdHeader);
}
/**
* Enable IO Cstate on a family 14h CPU.
* Implement steps 1 to 3 of BKDG section 2.5.4.2.9 BIOS Requirements for Initialization
*
* @param[in] IoCstateServices Pointer to this CPU's IO Cstate family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @return AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F14InitializeIoCstate (
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 i;
UINT32 MaxEnabledPstate;
UINT32 PciRegister;
UINT64 MsrRegister;
AP_TASK TaskPtr;
PCI_ADDR PciAddress;
if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
for (i = MSR_PSTATE_7; i > MSR_PSTATE_0; i--) {
LibAmdMsrRead (i, &MsrRegister, StdHeader);
if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
break;
}
}
MaxEnabledPstate = i - MSR_PSTATE_0;
// Initialize MSRC001_0073[CstateAddr] on each core to a region of
// the IO address map with 8 consecutive available addresses.
MsrRegister = 0;
((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
ASSERT ((((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr != 0) &&
(((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr <= 0xFFF8));
TaskPtr.FuncAddress.PfApTaskI = F14InitializeIoCstateOnCore;
TaskPtr.DataTransfer.DataSizeInDwords = 2;
TaskPtr.DataTransfer.DataPtr = &MsrRegister;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
// Program D18F4x1A8[PService] to the index of lowest-performance
// P-state with MSRC001_00[6B:64][PstateEn]==1 on core 0.
PciAddress.AddressValue = CPU_STATE_PM_CTRL0_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
((CPU_STATE_PM_CTRL0_REGISTER *) &PciRegister)->PService = MaxEnabledPstate;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
// Program D18F4x1AC[CstPminEn] to 1.
PciAddress.AddressValue = CPU_STATE_PM_CTRL1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
((CPU_STATE_PM_CTRL1_REGISTER *) &PciRegister)->CstPminEn = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
}
return AGESA_SUCCESS;
}
/**
* Main entry point for initializing the Thermal Control
* safety net feature.
*
* This must be run by all Family 16h Mullins core 0s in the system.
*
* @param[in] HtcServices The current CPU's family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F16MlInitializeHtc (
IN HTC_FAMILY_SERVICES *HtcServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
NB_CAPS_REGISTER NbCaps;
HTC_REGISTER HtcReg;
CLK_PWR_TIMING_CTRL2_REGISTER Cptc2;
POPUP_PSTATE_REGISTER PopUpPstate;
PCI_ADDR PciAddress;
D0F0xBC_xC0107097_STRUCT D0F0xBC_xC0107097;
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader);
if (NbCaps.HtcCapable == 1) {
// Enable HTC
PciAddress.Address.Register = HTC_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &HtcReg, StdHeader);
GnbRegisterReadML (GnbGetHandle (StdHeader), D0F0xBC_xC0107097_TYPE, D0F0xBC_xC0107097_ADDRESS, &D0F0xBC_xC0107097, 0, StdHeader);
HtcReg.HtcTmpLmt = D0F0xBC_xC0107097.Field.HtcTmpLmt;
if (HtcReg.HtcTmpLmt != 0) {
// Enable HTC
HtcReg.HtcEn = 1;
PciAddress.Address.Register = CPTC2_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2, StdHeader);
if (HtcReg.HtcPstateLimit > Cptc2.HwPstateMaxVal) {
// F3xDC[HwPstateMaxVal] = F3x64[HtcPstateLimit]
Cptc2.HwPstateMaxVal = HtcReg.HtcPstateLimit;
LibAmdPciWrite (AccessWidth32, PciAddress, &Cptc2, StdHeader);
// F3xA8[PopDownPstate] = F3xDC[HwPstateMaxVal]
PciAddress.Address.Register = POPUP_PSTATE_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &PopUpPstate, StdHeader);
PopUpPstate.PopDownPstate = Cptc2.HwPstateMaxVal;
LibAmdPciWrite (AccessWidth32, PciAddress, &PopUpPstate, StdHeader);
}
} else {
// Disable HTC
HtcReg.HtcEn = 0;
}
PciAddress.Address.Register = HTC_REG;
IDS_OPTION_HOOK (IDS_HTC_CTRL, &HtcReg, StdHeader);
LibAmdPciWrite (AccessWidth32, PciAddress, &HtcReg, StdHeader);
}
}
return AGESA_SUCCESS;
}
/**
* BSC entry point for for enabling Core Performance Boost.
*
* Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.
*
* @param[in] CpbServices The current CPU's family services.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] EntryPoint Current CPU feature dispatch point.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F15CzInitializeCpb (
IN CPB_FAMILY_SERVICES *CpbServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN UINT64 EntryPoint,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPB_CTRL_REGISTER CpbControl;
PCI_ADDR PciAddress;
PCI_ADDR StcPciAddr;
F15_PSTATE_MSR PstateMsrData;
SW_PS_LIMIT_REGISTER Stc;
UINT32 Pbx;
UINT32 PsMax;
if ((EntryPoint & CPU_FEAT_MID_INIT) != 0) {
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
if (CpbControl.BoostSrc == 0) {
// If any boosted P-state is still enabled, set BoostSrc = 1.
for (Pbx = 0; Pbx < CpbControl.NumBoostStates; Pbx++) {
LibAmdMsrRead (PS_REG_BASE + Pbx, (UINT64 *)&PstateMsrData, StdHeader);
if (PstateMsrData.PsEnable == 1) {
StcPciAddr.AddressValue = SW_PS_LIMIT_PCI_ADDR;
LibAmdPciRead (AccessWidth32, StcPciAddr, &Stc, StdHeader);
Stc.SwPstateLimitEn = 1;
Stc.SwPstateLimit = CpbControl.NumBoostStates;
LibAmdPciWrite (AccessWidth32, StcPciAddr, &Stc, StdHeader);
S3_SAVE_PCI_WRITE (StdHeader, StcPciAddr, AccessWidth32, &Stc);
CpbControl.BoostSrc = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader);
S3_SAVE_PCI_WRITE (StdHeader, PciAddress, AccessWidth32, &CpbControl);
break;
}
}
}
} else if ((EntryPoint & CPU_FEAT_MID_LATE_INIT) != 0) {
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 3, 0xDC);
LibAmdPciRead (AccessWidth32, PciAddress, &PsMax, StdHeader);
PsMax = ((PsMax & 0x700) << 20);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 3, 0x68);
LibAmdPciWrite (AccessWidth32, PciAddress, &PsMax, StdHeader);
S3_SAVE_PCI_WRITE (StdHeader, PciAddress, AccessWidth32, &PsMax);
}
return AGESA_SUCCESS;
}
/**
* Enable Cpu Cache Flush On Halt Function
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*/
VOID
SetF15KvCacheFlushOnHaltRegister (
IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
F15_KV_CLK_PWR_TIMING_CTRL2_REGISTER ClkPwrTimingCtrl2;
CSTATE_POLICY_CTRL1_REGISTER CstatePolicyCtrl1;
CSTATE_CTRL1_REGISTER CstateCtrl1;
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
// Set D18F3xDC[CacheFlushOnHaltCtl] != 0
// Set D18F3xDC[CacheFlushOnHaltTmr]
PciAddress.AddressValue = CPTC2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader);
ClkPwrTimingCtrl2.CacheFlushOnHaltCtl = 7;
ClkPwrTimingCtrl2.CacheFlushOnHaltTmr = 0x32;
LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader);
// Set D18F4x128[CacheFlushTmr, CacheFlushSucMonThreshold]
PciAddress.AddressValue = CSTATE_POLICY_CTRL1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader);
CstatePolicyCtrl1.CacheFlushTmr = 0x32;
CstatePolicyCtrl1.CacheFlushSucMonThreshold = 5;
CstatePolicyCtrl1.CacheFlushSucMonMispredictAct = 1;
CstatePolicyCtrl1.CacheFlushSucMonTmrSel = 0;
LibAmdPciWrite (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader);
// Set cache flush bits in D18F4x118
PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
// Set C-state Action Field 0
CstateCtrl1.CacheFlushEnCstAct0 = 1;
CstateCtrl1.CacheFlushTmrSelCstAct0 = 2;
CstateCtrl1.ClkDivisorCstAct0 = 0;
// Set C-state Action Field 1
CstateCtrl1.CacheFlushEnCstAct1 = 1;
CstateCtrl1.CacheFlushTmrSelCstAct1 = 1;
CstateCtrl1.ClkDivisorCstAct1 = 0;
LibAmdPciWrite (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
//Override the default setting
IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, NULL, StdHeader);
}
}
/**
* Enable Cpu Cache Flush On Halt Function
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*/
VOID
SetF16KbCacheFlushOnHaltRegister (
IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
CSTATE_CTRL1_REGISTER CstateCtrl1;
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
// Set F4x118
PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
// Set C-state Action Field 0
// bits[11] NbClkGate0 = 0x1
// bits[12] SelfRefr0 = 0x1
CstateCtrl1.NbClkGate0 = 1;
CstateCtrl1.SelfRefr0 = 1;
// Set C-state Action Field 1
// bits[27] NbClkGate1 = 0x1
// bits[28] SelfRefr1 = 0x1
CstateCtrl1.NbClkGate1 = 1;
CstateCtrl1.SelfRefr1 = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
//Override the default setting
IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, NULL, StdHeader);
}
}
/**
* Entry point for enabling Hardware Thermal Control
*
* This function must be run after all P-State routines have been executed
*
* @param[in] HtcServices The current CPU's family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F15KvInitializeHtc (
IN HTC_FAMILY_SERVICES *HtcServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 LocalPciRegister;
PCI_ADDR PciAddress;
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (((NB_CAPS_REGISTER *) &LocalPciRegister)->HtcCapable == 1) {
// Enable HTC
PciAddress.Address.Register = HTC_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (((HTC_REGISTER *) &LocalPciRegister)->HtcTmpLmt != 0) {
// Enable HTC
((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 1;
} else {
// Disable HTC
((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 0;
}
IDS_OPTION_HOOK (IDS_HTC_CTRL, &LocalPciRegister, StdHeader);
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
}
return AGESA_SUCCESS;
}
/**
* Main entry point for initializing the Thermal Control
* safety net feature.
*
* This must be run by all Family 10h core 0s in the system.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParamsPtr Service parameters.
* @param[in] StdHeader Config handle for library and services.
*/
VOID
F10PmThermalInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Core;
UINT32 Module;
UINT32 LocalPciRegister;
UINT32 Socket;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredSts;
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
ASSERT (Core == 0);
if (GetPciAddress (StdHeader, Socket, 0, &PciAddress, &IgnoredSts)) {
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = NB_CAPS_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (((NB_CAPS_REGISTER *) &LocalPciRegister)->HtcCapable == 1) {
// Enable HTC
PciAddress.Address.Register = HTC_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((HTC_REGISTER *) &LocalPciRegister)->HtcSlewSel = 0;
((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
}
}
/**
* BSC entry point for for enabling Core Performance Boost.
*
* Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.
*
* @param[in] CpbServices The current CPU's family services.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] EntryPoint Current CPU feature dispatch point.
* @param[in] Socket Zero based socket number to check.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F15TnInitializeCpb (
IN CPB_FAMILY_SERVICES *CpbServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN UINT64 EntryPoint,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPB_CTRL_REGISTER CpbControl;
PCI_ADDR PciAddress;
F15_PSTATE_MSR PstateMsrData;
UINT32 Pbx;
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
if ((CpbControl.BoostSrc == 0) && (CpbControl.NumBoostStates != 0)) {
// If any boosted P-state is still enabled, set BoostSrc = 1.
for (Pbx = 0; Pbx < CpbControl.NumBoostStates; Pbx++) {
LibAmdMsrRead (PS_REG_BASE + Pbx, (UINT64 *)&PstateMsrData, StdHeader);
if (PstateMsrData.PsEnable == 1) {
CpbControl.BoostSrc = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader);
break;
}
}
}
}
return AGESA_SUCCESS;
}
void imc_reg_init(void)
{
/* Init Power Management Block 2 (PM2) Registers.
* Check BKDG for AMD Family 16h for details. */
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x00, 0x06);
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x01, 0x06);
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x02, 0xf7);
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x03, 0xff);
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x04, 0xff);
#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x10, 0x06);
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x11, 0x06);
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x12, 0xf7);
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x13, 0xff);
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x14, 0xff);
#endif
#if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
UINT8 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 0x3, 0x1E4);
LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader);
PciData &= (UINT8)0x8F;
PciData |= 0x10;
LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader);
#endif
}
/**
* BSC entry point for for enabling Core Performance Boost.
*
* Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.
*
* @param[in] CpbServices The current CPU's family services.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] EntryPoint Current CPU feature dispatch point.
* @param[in] Socket Zero based socket number to check.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F12InitializeCpb (
IN CPB_FAMILY_SERVICES *CpbServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN UINT64 EntryPoint,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
D18F4x15C_STRUCT CpbControl;
SMUx0B_x8580_STRUCT SMUx0Bx8580;
if ((EntryPoint & CPU_FEAT_BEFORE_PM_INIT) != 0) {
// F12EarlySampleCpbSupport.F12CpbInitHook (StdHeader);
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl.Value, StdHeader);
CpbControl.Field.BoostSrc = 1;
IDS_OPTION_HOOK (IDS_CPB_CTRL, &CpbControl.Value, StdHeader);
LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl.Value, StdHeader);
} else if ((EntryPoint & CPU_FEAT_INIT_LATE_END) != 0) {
// Ensure that the recommended settings have been programmed into SMUx0B_x8580, then
// interrupt the SMU with service index 12h.
SMUx0Bx8580.Value = 0;
SMUx0Bx8580.Field.PdmPeriod = 0x1388;
SMUx0Bx8580.Field.PdmUnit = 1;
SMUx0Bx8580.Field.PdmCacEn = 1;
SMUx0Bx8580.Field.PdmEn = 1;
NbSmuRcuRegisterWrite (SMUx0B_x8580_ADDRESS, &SMUx0Bx8580.Value, 1, TRUE, StdHeader);
NbSmuServiceRequest (0x12, TRUE, StdHeader);
}
return AGESA_SUCCESS;
}
/**
* Enable config access to a non-coherent chain for the given bus range.
*
* @HtNbMethod{::F_SET_CONFIG_ADDR_MAP}
*
* @param[in] ConfigMapIndex the map entry to set
* @param[in] SecBus The secondary bus number to use
* @param[in] SubBus The subordinate bus number to use
* @param[in] TargetNode The Node that shall be the recipient of the traffic
* @param[in] TargetLink The Link that shall be the recipient of the traffic
* @param[in] State our global state
* @param[in] Nb this northbridge
*/
VOID
Fam10SetConfigAddrMap (
IN UINT8 ConfigMapIndex,
IN UINT8 SecBus,
IN UINT8 SubBus,
IN UINT8 TargetNode,
IN UINT8 TargetLink,
IN STATE_DATA *State,
IN NORTHBRIDGE *Nb
)
{
UINT8 CurNode;
PCI_ADDR Reg;
UINT32 Temp;
Reg = Nb->MakeLinkBase (TargetNode, TargetLink, Nb);
ASSERT (SecBus <= SubBus);
ASSERT (TargetNode <= State->NodesDiscovered);
ASSERT (TargetLink < Nb->MaxLinks);
Temp = SecBus;
Reg.Address.Register += HTHOST_ISOC_REG;
LibAmdPciWriteBits (Reg, 15, 8, &Temp, Nb->ConfigHandle);
Temp = ((UINT32)SubBus << 24) + ((UINT32)SecBus << 16) + ((UINT32)TargetLink << 8) +
((UINT32)TargetNode << 4) + (UINT32)3;
for (CurNode = 0; CurNode < (State->NodesDiscovered + 1); CurNode++) {
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (CurNode),
MakePciBusFromNode (CurNode),
MakePciDeviceFromNode (CurNode),
CPU_ADDR_FUNC_01,
REG_ADDR_CONFIG_MAP0_1XE0 + (4 * ConfigMapIndex));
LibAmdPciWrite (AccessWidth32, Reg, &Temp, Nb->ConfigHandle);
}
}
/**
* Set HT Frequency register for IO Devices
*
* Provide a common routine for accessing the HT Link Frequency registers at offset 8
* and 0x10, to enforce not clearing the HT Link error bits. Replaces direct use of
* AmdPCIWriteBits().
*
* @note This routine is called for IO Devices only!! All comply to the
* "HyperTransport I/O Link Specification ".
*
* @param[in] Reg the PCI config address the control register
* @param[in] Hibit the high bit number
* @param[in] Lobit the low bit number
* @param[in] Value the value to write to that bit range. Bit 0 => loBit.
* @param[in] State Our state, config handle for lib
*/
VOID
STATIC
SetHtIoFrequencyRegisterBits (
IN PCI_ADDR Reg,
IN UINT8 Hibit,
IN UINT8 Lobit,
IN UINT32 *Value,
IN STATE_DATA *State
)
{
UINT32 Mask;
UINT32 Temp;
ASSERT ((Hibit < 32) && (Lobit < 32) && (Hibit >= Lobit) && ((Reg.AddressValue & 0x3) == 0));
ASSERT ((Hibit < 12) || (Lobit > 14));
// A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
if ((Hibit - Lobit) != 31) {
Mask = (((UINT32)1 << ((Hibit - Lobit) + 1)) - 1);
} else {
Mask = (UINT32)0xFFFFFFFF;
}
LibAmdPciRead (AccessWidth32, Reg, &Temp, State->ConfigHandle);
Temp &= ~(Mask << Lobit);
Temp |= (*Value & Mask) << Lobit;
Temp &= (UINT32)HT_FREQUENCY_CLEAR_LINK_ERRORS;
LibAmdPciWrite (AccessWidth32, Reg, &Temp, State->ConfigHandle);
}
/**
* Writes to all nodes on the executing core's socket.
*
* @param[in] PciAddress The Function and Register to update
* @param[in] Mask The bitwise AND mask to apply to the current register value
* @param[in] Data The bitwise OR mask to apply to the current register value
* @param[in] StdHeader Header for library and services.
*
*/
VOID
ModifyCurrSocketPciMulti (
IN PCI_ADDR *PciAddress,
IN UINT32 Mask,
IN UINT32 Data,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Socket;
UINT32 Module;
UINT32 Core;
UINT32 LocalPciRegister;
AGESA_STATUS AgesaStatus;
PCI_ADDR Reg;
IdentifyCore (StdHeader, &Socket, &Module, &Core, &AgesaStatus);
for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &Reg, &AgesaStatus)) {
Reg.Address.Function = PciAddress->Address.Function;
Reg.Address.Register = PciAddress->Address.Register;
LibAmdPciRead (AccessWidth32, Reg, &LocalPciRegister, StdHeader);
LocalPciRegister &= Mask;
LocalPciRegister |= Data;
LibAmdPciWrite (AccessWidth32, Reg, &LocalPciRegister, StdHeader);
}
}
}
/**
* Access HT Link Control Register.
*
* @HtFeatMethod{::F_SET_HT_CONTROL_REGISTER_BITS}
*
* Provide a common routine for accessing the HT Link Control registers (84, a4, c4,
* e4), to enforce not clearing the HT CRC error bits. Replaces direct use of
* AmdPCIWriteBits().
*
* @note: This routine is called for CPUs as well as IO Devices! All comply to the
* "HyperTransport I/O Link Specification ".
*
* @param[in] Reg the PCI config address the control register
* @param[in] HiBit the high bit number
* @param[in] LoBit the low bit number
* @param[in] Value the value to write to that bit range. Bit 0 => loBit.
* @param[in] State Our state, config handle for lib
*/
VOID
SetHtControlRegisterBits (
IN PCI_ADDR Reg,
IN UINT8 HiBit,
IN UINT8 LoBit,
IN UINT32 *Value,
IN STATE_DATA *State
)
{
UINT32 Temp;
UINT32 mask;
ASSERT ((HiBit < 32) && (LoBit < 32) && (HiBit >= LoBit) && ((Reg.AddressValue & 0x3) == 0));
ASSERT ((HiBit < 8) || (LoBit > 9));
// A 1 << 32 == 1 << 0 due to x86 SHL instruction, so skip if that is the case
if ((HiBit - LoBit) != 31) {
mask = (((UINT32)1 << (HiBit - LoBit + 1)) - 1);
} else {
mask = (UINT32)0xFFFFFFFF;
}
LibAmdPciRead (AccessWidth32, Reg, &Temp, State->ConfigHandle);
Temp &= ~(mask << LoBit);
Temp |= (*Value & mask) << LoBit;
Temp &= (UINT32)HT_CONTROL_CLEAR_CRC;
LibAmdPciWrite (AccessWidth32, Reg, &Temp, State->ConfigHandle);
}
/**
* Hook before the probe filter initialization sequence.
*
* @param[in] HtAssistServices HT Assist family services.
* @param[in] Socket Processor socket to check.
* @param[in] StdHeader Config Handle for library, services.
*
*/
VOID
STATIC
F10HookBeforeInit (
IN HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Module;
UINT32 PciRegister;
UINT32 PfCtrlRegister;
PCI_ADDR PciAddress;
CPU_LOGICAL_ID LogicalId;
AGESA_STATUS IgnoredStatus;
UINT32 PackageType;
GetLogicalIdOfSocket (Socket, &LogicalId, StdHeader);
PackageType = LibAmdGetPackageType (StdHeader);
PciRegister = 0;
((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFWayNum = 2;
((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFSubCacheEn = 15;
((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFLoIndexHashEn = 1;
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = PROBE_FILTER_CTRL_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &PfCtrlRegister, StdHeader);
((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFPreferredSORepl =
((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFPreferredSORepl;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
// Assumption: all socket use the same CPU package.
if (((LogicalId.Revision & AMD_F10_D0) != 0) && (PackageType == PACKAGE_TYPE_C32)) {
// Apply erratum #384
// Set F2x11C[13:12] = 11b
PciAddress.Address.Function = FUNC_2;
PciAddress.Address.Register = 0x11C;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
PciRegister |= 0x3000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
}
}
}
}
/**
* BSC entry point for enabling Core Performance Boost.
*
* Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.
*
* @param[in] CpbServices The current CPU's family services.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] EntryPoint Current CPU feature dispatch point.
* @param[in] Socket Zero based socket number to check.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F14OnInitializeCpb (
IN CPB_FAMILY_SERVICES *CpbServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN UINT64 EntryPoint,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
CPB_CTRL_REGISTER CpbControl;
LPMV_SCALAR2_REGISTER LpmvScalar2;
SMUx0B_x8580_STRUCT SMUx0Bx8580;
if ((EntryPoint & CPU_FEAT_BEFORE_PM_INIT) != 0) {
// F4x14C [25:24] ApmCstExtPol = 1
PciAddress.AddressValue = LPMV_SCALAR2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LpmvScalar2, StdHeader);
LpmvScalar2.ApmCstExtPol = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &LpmvScalar2, StdHeader);
// F4x15C [1:0] BoostSrc = 1
// F4x15C [29] BoostEnAllCores = 1
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
CpbControl.BoostSrc = 1;
CpbControl.BoostEnAllCores = 1;
IDS_OPTION_HOOK (IDS_CPB_CTRL, &CpbControl, StdHeader);
LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader);
} else if ((EntryPoint & CPU_FEAT_INIT_LATE_END) != 0) {
// Ensure that the recommended settings have been programmed into SMUx0B_x8580, then
// interrupt the SMU with service index 12h.
NbSmuRcuRegisterRead (SMUx0B_x8580_ADDRESS, &SMUx0Bx8580.Value, 1, StdHeader);
SMUx0Bx8580.Field.PdmPeriod = 0x1388;
SMUx0Bx8580.Field.PdmParamLoc = 0;
SMUx0Bx8580.Field.PdmCacEn = 1;
SMUx0Bx8580.Field.PdmUnit = 1;
SMUx0Bx8580.Field.PdmEn = 1;
NbSmuRcuRegisterWrite (SMUx0B_x8580_ADDRESS, &SMUx0Bx8580.Value, 1, TRUE, StdHeader);
NbSmuServiceRequest (0x12, TRUE, StdHeader);
}
return AGESA_SUCCESS;
}
/**
* Support routine for F15OrPmNbAfterReset to perform MSR initialization on one
* core of each die in a family 15h socket.
*
* This function implements steps 1 - 13 on each core.
*
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
F15OrPmNbAfterResetOnCore (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 NbPsCtrlOnEntry;
UINT32 NbPsCtrlOnExit;
UINT64 LocalMsrRegister;
PCI_ADDR PciAddress;
// 1. Temp1 = D18F5x170[SwNbPstateLoDis].
// 2. Temp2 = D18F5x170[NbPstateDisOnP0].
// 3. Temp3 = D18F5x170[NbPstateThreshold].
OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
PciAddress.Address.Function = FUNC_5;
PciAddress.Address.Register = NB_PSTATE_CTRL;
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnEntry, StdHeader);
// Check if NB P-states were disabled, and if so, prevent any changes from occurring.
if (((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateMaxVal != 0) {
// 4. If MSRC001_0070[NbPstate] = 1, go to step 9
LibAmdMsrRead (MSR_COFVID_CTL, &LocalMsrRegister, StdHeader);
if (((COFVID_CTRL_MSR *) &LocalMsrRegister)->NbPstate == 0) {
// 5. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
// 6. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid,
// CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
TransitionToNbLow (PciAddress, StdHeader);
// 7. Set D18F5x170[SwNbPstateLoDis] = 1.
// 8. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid,
// CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi].
// Go to step 13.
TransitionToNbHigh (PciAddress, StdHeader);
} else {
// 9. Set D18F5x170[SwNbPstateLoDis] = 1.
// 10. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid,
// CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi].
TransitionToNbHigh (PciAddress, StdHeader);
// 11. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
// 12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid,
// CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
TransitionToNbLow (PciAddress, StdHeader);
}
// 13. Set D18F5x170[SwNbPstateLoDis] = Temp1, D18F5x170[NbPstateDisOnP0] = Temp2, and
// D18F5x170[NbPstateThreshold] = Temp3.
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader);
((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->SwNbPstateLoDis = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->SwNbPstateLoDis;
((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateDisOnP0 = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateDisOnP0;
((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateThreshold = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateThreshold;
LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader);
}
}
/**
* Save the current settings of the scrubbers, and disabled them.
*
* @param[in] HtAssistServices HT Assist family services.
* @param[in] Socket Processor socket to check.
* @param[in] ScrubSettings Location to store current L3 scrubber settings.
* @param[in] StdHeader Config Handle for library, services.
*
*/
VOID
STATIC
F10GetL3ScrubCtrl (
IN HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
IN UINT32 Socket,
IN UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE],
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Module;
UINT32 ScrubCtrl;
UINT32 ScrubAddr;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredStatus;
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
ASSERT (Module < L3_SCRUBBER_CONTEXT_ARRAY_SIZE);
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &ScrubAddr, StdHeader);
PciAddress.Address.Register = SCRUB_RATE_CTRL_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &ScrubCtrl, StdHeader);
((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->DramScrub =
((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->DramScrub;
((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->L3Scrub =
((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->L3Scrub;
((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->Redirect =
((DRAM_SCRUB_ADDR_LOW_REGISTER *) &ScrubAddr)->ScrubReDirEn;
((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->DramScrub = 0;
((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->L3Scrub = 0;
((DRAM_SCRUB_ADDR_LOW_REGISTER *) &ScrubAddr)->ScrubReDirEn = 0;
LibAmdPciWrite (AccessWidth32, PciAddress, &ScrubCtrl, StdHeader);
PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG;
LibAmdPciWrite (AccessWidth32, PciAddress, &ScrubAddr, StdHeader);
}
}
}
/**
* A Family Specific Workaround method, to sync internal node 1 SbiAddr setting.
*
* @param[in] Data The table data value (unused in this routine)
* @param[in] StdHeader Config handle for library and services
*
*---------------------------------------------------------------------------------------
**/
VOID
STATIC
F10RevDSyncInternalNode1SbiAddr (
IN UINT32 Data,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Socket;
UINT32 Module;
UINT32 DataOr;
UINT32 DataAnd;
UINT32 ModuleType;
PCI_ADDR PciAddress;
AGESA_STATUS AgesaStatus;
UINT32 SyncToModule;
AP_MAIL_INFO ApMailboxInfo;
UINT32 LocalPciRegister;
ApMailboxInfo.Info = 0;
GetApMailbox (&ApMailboxInfo.Info, StdHeader);
ASSERT (ApMailboxInfo.Fields.Socket < MAX_SOCKETS);
ASSERT (ApMailboxInfo.Fields.Module < MAX_DIES);
Socket = ApMailboxInfo.Fields.Socket;
Module = ApMailboxInfo.Fields.Module;
ModuleType = ApMailboxInfo.Fields.ModuleType;
// sync is just needed on multinode cpu
if (ModuleType != 0) {
// check if it is internal node 0 of every socket
if (Module == 0) {
if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) {
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = 0x1E4;
// read internal node 0 F3x1E4[6:4]
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
DataOr = LocalPciRegister & ((UINT32) (7 << 4));
DataAnd = ~(UINT32) (7 << 4);
for (SyncToModule = 1; SyncToModule < GetPlatformNumberOfModules (); SyncToModule++) {
if (GetPciAddress (StdHeader, Socket, SyncToModule, &PciAddress, &AgesaStatus)) {
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = 0x1E4;
// sync the other internal node F3x1E4[6:4]
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
LocalPciRegister &= DataAnd;
LocalPciRegister |= DataOr;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
}
}
}
}
}
static void setupFch(UINT16 ioBase)
{
AMD_CONFIG_PARAMS StdHeader;
UINT32 PciData32;
UINT8 PciData8;
PCI_ADDR PciAddress;
/* Set SMBus MMIO. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0x90);
PciData32 = (ioBase & 0xFFFFFFF0) | BIT0;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData32, &StdHeader);
/* Enable SMBus MMIO. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2);
LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ;
PciData8 |= BIT0;
LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader);
/* Set SMBus clock to 400 KHz */
__outbyte(ioBase + SMBUS_CLOCK_REG, SMBUS_FREQUENCY_CONST / 400000);
}
/**
*
* InitializeCacheFlushOnHaltFeature
*
* CPU feature leveling. Enable Cpu Cache Flush On Halt Function
*
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in,out] StdHeader Pointer to AMD_CONFIG_PARAMS struct.
*
* @return The most severe status of any family specific service.
*/
STATIC AGESA_STATUS
InitializeCacheFlushOnHaltFeature (
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Socket;
UINT32 Module;
UINT32 AndMask;
UINT32 OrMask;
UINT32 PciRegister;
PCI_ADDR PciAddress;
PCI_ADDR CfohPciAddress;
AGESA_STATUS AgesaStatus;
CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices;
ASSERT (IsBsp (StdHeader, &AgesaStatus));
FamilySpecificServices = NULL;
AndMask = 0xFFFFFFFF;
OrMask = 0x00000000;
PciRegister = 0;
AgesaStatus = AGESA_SUCCESS;
for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
// Get services for the socket
GetFeatureServicesOfSocket (&CacheFlushOnHaltFamilyServiceTable, Socket, (CONST VOID **)&FamilySpecificServices, StdHeader);
if (FamilySpecificServices != NULL) {
FamilySpecificServices->GetCacheFlushOnHaltRegister (FamilySpecificServices, &CfohPciAddress, &AndMask, &OrMask, StdHeader);
// Get the Or Mask value from IDS
IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, &OrMask, StdHeader);
// Set Cache Flush On Halt register
for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) {
PciAddress.Address.Function = CfohPciAddress.Address.Function;
PciAddress.Address.Register = CfohPciAddress.Address.Register;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
PciRegister &= AndMask;
PciRegister |= OrMask;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
}
}
}
}
}
return AgesaStatus;
}
VOID
WritePci (
IN UINT32 Address,
IN UINT8 OpFlag,
IN VOID *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
PciAddress.AddressValue = ((Address >> 4) & ~0xFFF) + (Address & 0xFFF);
LibAmdPciWrite ((ACCESS_WIDTH) OpFlag, PciAddress, Value, StdHeader);
}
/**
* Enable the Probe filter feature.
*
* @param[in] HtAssistServices HT Assist family services.
* @param[in] Socket Processor socket to check.
* @param[in] StdHeader Config Handle for library, services.
*
*/
VOID
STATIC
F10HtAssistInit (
IN HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Module;
UINT32 PciRegister;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredStatus;
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = L3_CACHE_PARAM_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
((L3_CACHE_PARAM_REGISTER *) &PciRegister)->L3TagInit = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
do {
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
} while (((L3_CACHE_PARAM_REGISTER *) &PciRegister)->L3TagInit != 0);
PciAddress.Address.Register = PROBE_FILTER_CTRL_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFMode = 0;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
F10RevDProbeFilterCritical (PciAddress, PciRegister);
do {
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
} while (((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFInitDone != 1);
IDS_OPTION_HOOK (IDS_HT_ASSIST, &PciAddress, StdHeader);
}
}
}
/** RwXhciIndReg - Reserved **/
VOID
RwXhciIndReg (
IN UINT32 Index,
IN UINT32 AndMask,
IN UINT32 OrMask,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 RevReg;
PCI_ADDR PciAddress;
PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x48;
LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader);
PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x4C;
RevReg = ~AndMask;
LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader);
PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x48;
LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader);
PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x4C;
RevReg = ~AndMask;
LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader);
}
