static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
{
unsigned long netctl;
unsigned long netstat;
unsigned long frame;
netctl = macb_readl(macb, NCR);
netctl |= MACB_BIT(MPE);
macb_writel(macb, NCR, netctl);
frame = (MACB_BF(SOF, 1)
| MACB_BF(RW, 2)
| MACB_BF(PHYA, macb->phy_addr)
| MACB_BF(REGA, reg)
| MACB_BF(CODE, 2));
macb_writel(macb, MAN, frame);
do {
netstat = macb_readl(macb, NSR);
} while (!(netstat & MACB_BIT(IDLE)));
frame = macb_readl(macb, MAN);
netctl = macb_readl(macb, NCR);
netctl &= ~MACB_BIT(MPE);
macb_writel(macb, NCR, netctl);
return MACB_BFEXT(DATA, frame);
}
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
{
struct macb_device *macb;
struct eth_device *netdev;
unsigned long macb_hz;
u32 ncfgr;
macb = malloc(sizeof(struct macb_device));
if (!macb) {
printf("Error: Failed to allocate memory for MACB%d\n", id);
return -1;
}
memset(macb, 0, sizeof(struct macb_device));
netdev = &macb->netdev;
macb->rx_buffer = dma_alloc_coherent(CONFIG_SYS_MACB_RX_BUFFER_SIZE,
&macb->rx_buffer_dma);
macb->rx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_RX_RING_SIZE
* sizeof(struct macb_dma_desc),
&macb->rx_ring_dma);
macb->tx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_TX_RING_SIZE
* sizeof(struct macb_dma_desc),
&macb->tx_ring_dma);
macb->regs = regs;
macb->phy_addr = phy_addr;
sprintf(netdev->name, "macb%d", id);
netdev->init = macb_init;
netdev->halt = macb_halt;
netdev->send = macb_send;
netdev->recv = macb_recv;
netdev->write_hwaddr = macb_write_hwaddr;
/*
* Do some basic initialization so that we at least can talk
* to the PHY
*/
macb_hz = get_macb_pclk_rate(id);
if (macb_hz < 20000000)
ncfgr = MACB_BF(CLK, MACB_CLK_DIV8);
else if (macb_hz < 40000000)
ncfgr = MACB_BF(CLK, MACB_CLK_DIV16);
else if (macb_hz < 80000000)
ncfgr = MACB_BF(CLK, MACB_CLK_DIV32);
else
ncfgr = MACB_BF(CLK, MACB_CLK_DIV64);
macb_writel(macb, NCFGR, ncfgr);
eth_register(netdev);
#if defined(CONFIG_CMD_MII)
miiphy_register(netdev->name, macb_miiphy_read, macb_miiphy_write);
#endif
return 0;
}
static int macb_phy_read(struct mii_device *mdev, int addr, int reg)
{
struct eth_device *edev = mdev->edev;
struct macb_device *macb = edev->priv;
unsigned long netctl;
unsigned long netstat;
unsigned long frame;
int iflag;
int value;
uint64_t start;
debug("%s\n", __func__);
iflag = disable_interrupts();
netctl = readl(macb->regs + MACB_NCR);
netctl |= MACB_BIT(MPE);
writel(netctl, macb->regs + MACB_NCR);
if (iflag)
enable_interrupts();
frame = (MACB_BF(SOF, 1)
| MACB_BF(RW, 2)
| MACB_BF(PHYA, addr)
| MACB_BF(REGA, reg)
| MACB_BF(CODE, 2));
writel(frame, macb->regs + MACB_MAN);
start = get_time_ns();
do {
netstat = readl(macb->regs + MACB_NSR);
if (is_timeout(start, SECOND)) {
printf("phy read timed out\n");
return -1;
}
} while (!(netstat & MACB_BIT(IDLE)));
frame = readl(macb->regs + MACB_MAN);
value = MACB_BFEXT(DATA, frame);
iflag = disable_interrupts();
netctl = readl(macb->regs + MACB_NCR);
netctl &= ~MACB_BIT(MPE);
writel(netctl, macb->regs + MACB_NCR);
if (iflag)
enable_interrupts();
return value;
}
static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
{
u32 config;
unsigned long macb_hz = get_macb_pclk_rate(id);
if (macb_hz < 20000000)
config = MACB_BF(CLK, MACB_CLK_DIV8);
else if (macb_hz < 40000000)
config = MACB_BF(CLK, MACB_CLK_DIV16);
else if (macb_hz < 80000000)
config = MACB_BF(CLK, MACB_CLK_DIV32);
else
config = MACB_BF(CLK, MACB_CLK_DIV64);
return config;
}
static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
{
u32 config;
#if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
unsigned long macb_hz = macb->pclk_rate;
#else
unsigned long macb_hz = get_macb_pclk_rate(id);
#endif
if (macb_hz < 20000000)
config = MACB_BF(CLK, MACB_CLK_DIV8);
else if (macb_hz < 40000000)
config = MACB_BF(CLK, MACB_CLK_DIV16);
else if (macb_hz < 80000000)
config = MACB_BF(CLK, MACB_CLK_DIV32);
else
config = MACB_BF(CLK, MACB_CLK_DIV64);
return config;
}
int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
{
unsigned long netctl;
unsigned long netstat;
unsigned long frame;
int iflag;
iflag = disable_interrupts();
netctl = macb_readl(&macb, EMACB_NCR);
netctl |= MACB_BIT(MPE);
macb_writel(&macb, EMACB_NCR, netctl);
if (iflag)
enable_interrupts();
frame = (MACB_BF(SOF, 1)
| MACB_BF(RW, 1)
| MACB_BF(PHYA, addr)
| MACB_BF(REGA, reg)
| MACB_BF(CODE, 2)
| MACB_BF(DATA, value));
macb_writel(&macb, EMACB_MAN, frame);
do {
netstat = macb_readl(&macb, EMACB_NSR);
} while (!(netstat & MACB_BIT(IDLE)));
iflag = disable_interrupts();
netctl = macb_readl(&macb, EMACB_NCR);
netctl &= ~MACB_BIT(MPE);
macb_writel(&macb, EMACB_NCR, netctl);
if (iflag)
enable_interrupts();
return 0;
}
static int macb_phy_write(struct mii_device *mdev, int addr, int reg, int value)
{
struct eth_device *edev = mdev->edev;
struct macb_device *macb = edev->priv;
unsigned long netctl;
unsigned long netstat;
unsigned long frame;
debug("%s\n", __func__);
netctl = readl(macb->regs + MACB_NCR);
netctl |= MACB_BIT(MPE);
writel(netctl, macb->regs + MACB_NCR);
frame = (MACB_BF(SOF, 1)
| MACB_BF(RW, 1)
| MACB_BF(PHYA, addr)
| MACB_BF(REGA, reg)
| MACB_BF(CODE, 2)
| MACB_BF(DATA, value));
writel(frame, macb->regs + MACB_MAN);
do {
netstat = readl(macb->regs + MACB_NSR);
} while (!(netstat & MACB_BIT(IDLE)));
netctl = readl(macb->regs + MACB_NCR);
netctl &= ~MACB_BIT(MPE);
writel(netctl, macb->regs + MACB_NCR);
return 0;
}
static void macb_smi_write(struct macb_device *macb, u16 phy, u8 reg, u16 value)
{
unsigned long netctl;
unsigned long netstat;
unsigned long frame;
netctl = macb_readl(macb, NCR);
netctl |= MACB_BIT(MPE);
macb_writel(macb, NCR, netctl);
frame = (MACB_BF(SOF, 1)
| MACB_BF(RW, 1)
| MACB_BF(PHYA, phy)
| MACB_BF(REGA, reg)
| MACB_BF(CODE, 2)
| MACB_BF(DATA, value));
macb_writel(macb, MAN, frame);
do {
netstat = macb_readl(macb, NSR);
} while (!(netstat & MACB_BIT(IDLE)));
netctl = macb_readl(macb, NCR);
netctl &= ~MACB_BIT(MPE);
macb_writel(macb, NCR, netctl);
}
/* Extract received frame from buffer descriptors and sent to upper layers.
* (Called from interrupt context)
*/
static void at91ether_rx(struct net_device *dev)
{
struct macb *lp = netdev_priv(dev);
unsigned char *p_recv;
struct sk_buff *skb;
unsigned int pktlen;
while (lp->rx_ring[lp->rx_tail].addr & MACB_BIT(RX_USED)) {
p_recv = lp->rx_buffers + lp->rx_tail * MAX_RBUFF_SZ;
pktlen = MACB_BF(RX_FRMLEN, lp->rx_ring[lp->rx_tail].ctrl);
skb = netdev_alloc_skb(dev, pktlen + 2);
if (skb) {
skb_reserve(skb, 2);
memcpy(skb_put(skb, pktlen), p_recv, pktlen);
skb->protocol = eth_type_trans(skb, dev);
lp->stats.rx_packets++;
lp->stats.rx_bytes += pktlen;
netif_rx(skb);
} else {
lp->stats.rx_dropped++;
netdev_notice(dev, "Memory squeeze, dropping packet.\n");
}
if (lp->rx_ring[lp->rx_tail].ctrl & MACB_BIT(RX_MHASH_MATCH))
lp->stats.multicast++;
/* reset ownership bit */
lp->rx_ring[lp->rx_tail].addr &= ~MACB_BIT(RX_USED);
/* wrap after last buffer */
if (lp->rx_tail == MAX_RX_DESCR - 1)
lp->rx_tail = 0;
else
lp->rx_tail++;
}
}
/* Detect MAC & PHY and perform ethernet interface initialization */
static int __init at91ether_probe(struct platform_device *pdev)
{
struct macb_platform_data *board_data = dev_get_platdata(&pdev->dev);
struct resource *regs;
struct net_device *dev;
struct phy_device *phydev;
struct macb *lp;
int res;
u32 reg;
const char *mac;
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!regs)
return -ENOENT;
dev = alloc_etherdev(sizeof(struct macb));
if (!dev)
return -ENOMEM;
lp = netdev_priv(dev);
lp->pdev = pdev;
lp->dev = dev;
spin_lock_init(&lp->lock);
/* physical base address */
dev->base_addr = regs->start;
lp->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
if (!lp->regs) {
res = -ENOMEM;
goto err_free_dev;
}
/* Clock */
lp->pclk = devm_clk_get(&pdev->dev, "ether_clk");
if (IS_ERR(lp->pclk)) {
res = PTR_ERR(lp->pclk);
goto err_free_dev;
}
clk_enable(lp->pclk);
lp->hclk = ERR_PTR(-ENOENT);
lp->tx_clk = ERR_PTR(-ENOENT);
/* Install the interrupt handler */
dev->irq = platform_get_irq(pdev, 0);
res = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt, 0, dev->name, dev);
if (res)
goto err_disable_clock;
ether_setup(dev);
dev->netdev_ops = &at91ether_netdev_ops;
dev->ethtool_ops = &macb_ethtool_ops;
platform_set_drvdata(pdev, dev);
SET_NETDEV_DEV(dev, &pdev->dev);
mac = of_get_mac_address(pdev->dev.of_node);
if (mac)
memcpy(lp->dev->dev_addr, mac, ETH_ALEN);
else
macb_get_hwaddr(lp);
res = of_get_phy_mode(pdev->dev.of_node);
if (res < 0) {
if (board_data && board_data->is_rmii)
lp->phy_interface = PHY_INTERFACE_MODE_RMII;
else
lp->phy_interface = PHY_INTERFACE_MODE_MII;
} else {
lp->phy_interface = res;
}
macb_writel(lp, NCR, 0);
reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
if (lp->phy_interface == PHY_INTERFACE_MODE_RMII)
reg |= MACB_BIT(RM9200_RMII);
macb_writel(lp, NCFGR, reg);
/* Register the network interface */
res = register_netdev(dev);
if (res)
goto err_disable_clock;
res = macb_mii_init(lp);
if (res)
goto err_out_unregister_netdev;
/* will be enabled in open() */
netif_carrier_off(dev);
phydev = lp->phy_dev;
netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
phydev->drv->name, dev_name(&phydev->dev),
phydev->irq);
/* Display ethernet banner */
netdev_info(dev, "AT91 ethernet at 0x%08lx int=%d (%pM)\n",
dev->base_addr, dev->irq, dev->dev_addr);
return 0;
err_out_unregister_netdev:
unregister_netdev(dev);
err_disable_clock:
clk_disable(lp->pclk);
err_free_dev:
free_netdev(dev);
return res;
}
static int macb_probe(struct device_d *dev)
{
struct eth_device *edev;
struct macb_device *macb;
unsigned long macb_hz;
u32 ncfgr;
struct at91_ether_platform_data *pdata;
#if defined(CONFIG_ARCH_AT91)
struct clk *pclk;
#endif
if (!dev->platform_data) {
printf("macb: no platform_data\n");
return -ENODEV;
}
pdata = dev->platform_data;
edev = xzalloc(sizeof(struct eth_device) + sizeof(struct macb_device));
dev->type_data = edev;
edev->priv = (struct macb_device *)(edev + 1);
macb = edev->priv;
edev->init = macb_init;
edev->open = macb_open;
edev->send = macb_send;
edev->recv = macb_recv;
edev->halt = macb_halt;
edev->get_ethaddr = macb_get_ethaddr;
edev->set_ethaddr = macb_set_ethaddr;
macb->miidev.read = macb_phy_read;
macb->miidev.write = macb_phy_write;
macb->miidev.address = pdata->phy_addr;
macb->miidev.flags = pdata->flags & AT91SAM_ETHER_FORCE_LINK ?
MIIDEV_FORCE_LINK : 0;
macb->miidev.edev = edev;
macb->flags = pdata->flags;
macb->rx_buffer = xmalloc(CFG_MACB_RX_BUFFER_SIZE);
macb->rx_ring = xmalloc(CFG_MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
macb->tx_ring = xmalloc(sizeof(struct macb_dma_desc));
macb->regs = (void *)dev->map_base;
/*
* Do some basic initialization so that we at least can talk
* to the PHY
*/
#if defined(CONFIG_ARCH_AT91)
pclk = clk_get(dev, "macb_clk");
clk_enable(pclk);
macb_hz = clk_get_rate(pclk);
#else
macb_hz = get_macb_pclk_rate(0);
#endif
if (macb_hz < 20000000)
ncfgr = MACB_BF(CLK, MACB_CLK_DIV8);
else if (macb_hz < 40000000)
ncfgr = MACB_BF(CLK, MACB_CLK_DIV16);
else if (macb_hz < 80000000)
ncfgr = MACB_BF(CLK, MACB_CLK_DIV32);
else
ncfgr = MACB_BF(CLK, MACB_CLK_DIV64);
writel(ncfgr, macb->regs + MACB_NCFGR);
mii_register(&macb->miidev);
eth_register(edev);
return 0;
}
