/* Starts a PHY write via the MII */
void IP_ENET_StartMIIWrite(IP_ENET_001_Type *LPC_ENET, uint8_t reg, uint16_t data)
{
/* Write value at PHY address and register */
LPC_ENET->MAC_MII_ADDR = phyCfg | MAC_MIIA_GR(reg) | MAC_MIIA_W;
LPC_ENET->MAC_MII_DATA = (uint32_t) data;
LPC_ENET->MAC_MII_ADDR |= MAC_MIIA_GB;
}
/* Starts a read operation via the MII link (non-blocking) */
void lpc_mii_read_noblock(u32_t PhyReg)
{
/* Read value at PHY address and register */
LPC_ETHERNET->MAC_MII_ADDR = MAC_MIIA_PA(LPC_PHYDEF_PHYADDR) |
MAC_MIIA_GR(PhyReg) | MAC_MIIA_CR(4);
LPC_ETHERNET->MAC_MII_ADDR |= MAC_MIIA_GB;
}
/* Starts a PHY write via the MII */
void Chip_ENET_StartMIIWrite(LPC_ENET_T *pENET, uint8_t reg, uint16_t data)
{
/* Write value at PHY address and register */
pENET->MAC_MII_ADDR = phyCfg | MAC_MIIA_GR(reg) | MAC_MIIA_W;
pENET->MAC_MII_DATA = (uint32_t) data;
pENET->MAC_MII_ADDR |= MAC_MIIA_GB;
}
/* Write a value via the MII link (non-blocking) */
void lpc_mii_write_noblock(u32_t PhyReg, u32_t Value)
{
/* Write value at PHY address and register */
LPC_ETHERNET->MAC_MII_ADDR = MAC_MIIA_PA(LPC_PHYDEF_PHYADDR) |
MAC_MIIA_GR(PhyReg) | MAC_MIIA_CR(4) | MAC_MIIA_W;
LPC_ETHERNET->MAC_MII_DATA = Value;
LPC_ETHERNET->MAC_MII_ADDR |= MAC_MIIA_GB;
}
/*Starts a PHY read via the MII */
void IP_ENET_StartMIIRead(IP_ENET_001_Type *LPC_ENET, uint8_t reg)
{
/* Read value at PHY address and register */
LPC_ENET->MAC_MII_ADDR = phyCfg | MAC_MIIA_GR(reg);
LPC_ENET->MAC_MII_ADDR |= MAC_MIIA_GB;
}
/*Starts a PHY read via the MII */
void Chip_ENET_StartMIIRead(LPC_ENET_T *pENET, uint8_t reg)
{
/* Read value at PHY address and register */
pENET->MAC_MII_ADDR = phyCfg | MAC_MIIA_GR(reg);
pENET->MAC_MII_ADDR |= MAC_MIIA_GB;
}