int mac_receive(void)
{
PSRxDesc pRD;
int length = 0, tmp;
DWORD isr_status;
/* 1.store ISR */
MACvReadISR(sg_aAdapter->dwIoBase, sg_aAdapter->byRevId, &isr_status);
/* 2.disable IMR */
MACvIntDisable(sg_aAdapter->dwIoBase, sg_aAdapter->byRevId);
/* 3clear ISR */
MACvWriteISR(sg_aAdapter->dwIoBase, sg_aAdapter->byRevId, isr_status);
/* 4.handle ISR */
/* 5.handle received packets until owner==chip */
/* printf("enter mac_receive\n"); */
while (TRUE) {
pRD = sg_aAdapter->apRD[sg_aAdapter->idxRxCurDesc];
/* a.check RD status */
/* if owner==chip break; */
if (pRD->m_rd0RD0.f1Owner == B_OWNED_BY_CHIP) {
/* printf("receive done \n"); */
break;
}
/* if ok, net_receive() */
if (pRD->m_rd0RD0.byRSR1&RSR1_RXOK) {
NetReceive((volatile uchar *)pRD->m_dwRxBufferAddr, pRD->m_rd0RD0.f15FrameLen-4);
length += (pRD->m_rd0RD0.f15FrameLen-4);
#if MACDBG
printf("receive ok\n");
#endif
} else {
/* else, error handling */
printf("receive error status:%02X %02X%\n",
pRD->m_rd0RD0.byRSR1,
pRD->m_rd0RD0.byRSR0);
/* handler will do later */
}
/* b.set own==chip */
pRD->m_rd0RD0.f1Owner = B_OWNED_BY_CHIP;
/* c.increase to next RD */
tmp = (++sg_aAdapter->idxRxCurDesc);
sg_aAdapter->idxRxCurDesc = tmp % sg_aAdapter->cbRD;
#if MACDBG
printf("jump to next RD =%d\n", sg_aAdapter->idxRxCurDesc);
#endif
}
/* 6.enable IMR */
MACvIntEnable(sg_aAdapter->dwIoBase, sg_aAdapter->byRevId, IMR_MASK_VALUE);
return length;
}
static irqreturn_t device_intr(int irq, void *dev_instance)
{
struct vnt_private *pDevice = dev_instance;
int max_count = 0;
unsigned long dwMIBCounter = 0;
unsigned char byOrgPageSel = 0;
int handled = 0;
unsigned long flags;
MACvReadISR(pDevice->PortOffset, &pDevice->dwIsr);
if (pDevice->dwIsr == 0)
return IRQ_RETVAL(handled);
if (pDevice->dwIsr == 0xffffffff) {
pr_debug("dwIsr = 0xffff\n");
return IRQ_RETVAL(handled);
}
handled = 1;
MACvIntDisable(pDevice->PortOffset);
spin_lock_irqsave(&pDevice->lock, flags);
//Make sure current page is 0
VNSvInPortB(pDevice->PortOffset + MAC_REG_PAGE1SEL, &byOrgPageSel);
if (byOrgPageSel == 1)
MACvSelectPage0(pDevice->PortOffset);
else
byOrgPageSel = 0;
MACvReadMIBCounter(pDevice->PortOffset, &dwMIBCounter);
// TBD....
// Must do this after doing rx/tx, cause ISR bit is slow
// than RD/TD write back
// update ISR counter
STAvUpdate802_11Counter(&pDevice->s802_11Counter, &pDevice->scStatistic, dwMIBCounter);
while (pDevice->dwIsr != 0) {
STAvUpdateIsrStatCounter(&pDevice->scStatistic, pDevice->dwIsr);
MACvWriteISR(pDevice->PortOffset, pDevice->dwIsr);
if (pDevice->dwIsr & ISR_FETALERR) {
pr_debug(" ISR_FETALERR\n");
VNSvOutPortB(pDevice->PortOffset + MAC_REG_SOFTPWRCTL, 0);
VNSvOutPortW(pDevice->PortOffset + MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPECTI);
device_error(pDevice, pDevice->dwIsr);
}
if (pDevice->dwIsr & ISR_TBTT) {
if (pDevice->vif &&
pDevice->op_mode != NL80211_IFTYPE_ADHOC)
vnt_check_bb_vga(pDevice);
pDevice->bBeaconSent = false;
if (pDevice->bEnablePSMode)
PSbIsNextTBTTWakeUp((void *)pDevice);
if ((pDevice->op_mode == NL80211_IFTYPE_AP ||
pDevice->op_mode == NL80211_IFTYPE_ADHOC) &&
pDevice->vif->bss_conf.enable_beacon) {
MACvOneShotTimer1MicroSec(pDevice->PortOffset,
(pDevice->vif->bss_conf.beacon_int - MAKE_BEACON_RESERVED) << 10);
}
/* TODO: adhoc PS mode */
}
if (pDevice->dwIsr & ISR_BNTX) {
if (pDevice->op_mode == NL80211_IFTYPE_ADHOC) {
pDevice->bIsBeaconBufReadySet = false;
pDevice->cbBeaconBufReadySetCnt = 0;
}
pDevice->bBeaconSent = true;
}
if (pDevice->dwIsr & ISR_RXDMA0)
max_count += device_rx_srv(pDevice, TYPE_RXDMA0);
if (pDevice->dwIsr & ISR_RXDMA1)
max_count += device_rx_srv(pDevice, TYPE_RXDMA1);
if (pDevice->dwIsr & ISR_TXDMA0)
max_count += device_tx_srv(pDevice, TYPE_TXDMA0);
if (pDevice->dwIsr & ISR_AC0DMA)
max_count += device_tx_srv(pDevice, TYPE_AC0DMA);
if (pDevice->dwIsr & ISR_SOFTTIMER1) {
if (pDevice->vif) {
if (pDevice->vif->bss_conf.enable_beacon)
vnt_beacon_make(pDevice, pDevice->vif);
}
}
/* If both buffers available wake the queue */
if (pDevice->vif) {
if (AVAIL_TD(pDevice, TYPE_TXDMA0) &&
AVAIL_TD(pDevice, TYPE_AC0DMA) &&
ieee80211_queue_stopped(pDevice->hw, 0))
ieee80211_wake_queues(pDevice->hw);
}
MACvReadISR(pDevice->PortOffset, &pDevice->dwIsr);
MACvReceive0(pDevice->PortOffset);
MACvReceive1(pDevice->PortOffset);
if (max_count > pDevice->sOpts.int_works)
break;
}
if (byOrgPageSel == 1)
MACvSelectPage1(pDevice->PortOffset);
spin_unlock_irqrestore(&pDevice->lock, flags);
MACvIntEnable(pDevice->PortOffset, IMR_MASK_VALUE);
return IRQ_RETVAL(handled);
}
static void vnt_interrupt_process(struct vnt_private *priv)
{
struct ieee80211_low_level_stats *low_stats = &priv->low_stats;
int max_count = 0;
u32 mib_counter;
u32 isr;
unsigned long flags;
MACvReadISR(priv->PortOffset, &isr);
if (isr == 0)
return;
if (isr == 0xffffffff) {
pr_debug("isr = 0xffff\n");
return;
}
MACvIntDisable(priv->PortOffset);
spin_lock_irqsave(&priv->lock, flags);
/* Read low level stats */
MACvReadMIBCounter(priv->PortOffset, &mib_counter);
low_stats->dot11RTSSuccessCount += mib_counter & 0xff;
low_stats->dot11RTSFailureCount += (mib_counter >> 8) & 0xff;
low_stats->dot11ACKFailureCount += (mib_counter >> 16) & 0xff;
low_stats->dot11FCSErrorCount += (mib_counter >> 24) & 0xff;
/*
* TBD....
* Must do this after doing rx/tx, cause ISR bit is slow
* than RD/TD write back
* update ISR counter
*/
while (isr && priv->vif) {
MACvWriteISR(priv->PortOffset, isr);
if (isr & ISR_FETALERR) {
pr_debug(" ISR_FETALERR\n");
VNSvOutPortB(priv->PortOffset + MAC_REG_SOFTPWRCTL, 0);
VNSvOutPortW(priv->PortOffset +
MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPECTI);
device_error(priv, isr);
}
if (isr & ISR_TBTT) {
if (priv->op_mode != NL80211_IFTYPE_ADHOC)
vnt_check_bb_vga(priv);
priv->bBeaconSent = false;
if (priv->bEnablePSMode)
PSbIsNextTBTTWakeUp((void *)priv);
if ((priv->op_mode == NL80211_IFTYPE_AP ||
priv->op_mode == NL80211_IFTYPE_ADHOC) &&
priv->vif->bss_conf.enable_beacon) {
MACvOneShotTimer1MicroSec(priv->PortOffset,
(priv->vif->bss_conf.beacon_int - MAKE_BEACON_RESERVED) << 10);
}
/* TODO: adhoc PS mode */
}
if (isr & ISR_BNTX) {
if (priv->op_mode == NL80211_IFTYPE_ADHOC) {
priv->bIsBeaconBufReadySet = false;
priv->cbBeaconBufReadySetCnt = 0;
}
priv->bBeaconSent = true;
}
if (isr & ISR_RXDMA0)
max_count += device_rx_srv(priv, TYPE_RXDMA0);
if (isr & ISR_RXDMA1)
max_count += device_rx_srv(priv, TYPE_RXDMA1);
if (isr & ISR_TXDMA0)
max_count += device_tx_srv(priv, TYPE_TXDMA0);
if (isr & ISR_AC0DMA)
max_count += device_tx_srv(priv, TYPE_AC0DMA);
if (isr & ISR_SOFTTIMER1) {
if (priv->vif->bss_conf.enable_beacon)
vnt_beacon_make(priv, priv->vif);
}
/* If both buffers available wake the queue */
if (AVAIL_TD(priv, TYPE_TXDMA0) &&
AVAIL_TD(priv, TYPE_AC0DMA) &&
ieee80211_queue_stopped(priv->hw, 0))
ieee80211_wake_queues(priv->hw);
MACvReadISR(priv->PortOffset, &isr);
MACvReceive0(priv->PortOffset);
MACvReceive1(priv->PortOffset);
if (max_count > priv->sOpts.int_works)
break;
}
spin_unlock_irqrestore(&priv->lock, flags);
MACvIntEnable(priv->PortOffset, IMR_MASK_VALUE);
}