示例#1
0
/*!
 *  ======== InterruptDsp_intPost ========
 */
Void InterruptDsp_intPost(UInt16 srcProcId, IInterrupt_IntInfo *intInfo, 
                          UArg arg)
{
    UInt key;
    
    if (srcProcId == InterruptDsp_vpssProcId) {
        key = Hwi_disable();
        if (REG32(MAILBOX_STATUS(VPSS_TO_DSP)) == 0) {
            REG32(MAILBOX_MESSAGE(VPSS_TO_DSP)) = arg;
        }
        Hwi_restore(key);
    }
    else if (srcProcId == InterruptDsp_videoProcId) {
        key = Hwi_disable();
        if (REG32(MAILBOX_STATUS(VIDEO_TO_DSP)) == 0) {
            REG32(MAILBOX_MESSAGE(VIDEO_TO_DSP)) = arg;
        }
        Hwi_restore(key);
    }
    else {  /* hostProcId */
        key = Hwi_disable();
        if (REG32(MAILBOX_STATUS(HOST_TO_DSP)) == 0) {
            REG32(MAILBOX_MESSAGE(HOST_TO_DSP)) = arg;
        }
        Hwi_restore(key);
    }
}
示例#2
0
/*!
 *  ======== InterruptDsp_intSend ========
 *  Send interrupt to the remote processor
 */
Void InterruptDsp_intSend(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo, 
                          UArg arg)
{
    UInt key;
    
    /* 
     *  Before writing to a mailbox, check whehter it already contains a message
     *  If so, then don't write to the mailbox since we want one and only one
     *  message per interrupt.  Disable interrupts between reading 
     *  the MSGSTATUS_X register and writing to the mailbox to protect from 
     *  another thread doing an intSend at the same time
     */
    if (remoteProcId == InterruptDsp_hostProcId) {
        /* Using mailbox 0 */
        key = Hwi_disable();
        if (REG32(MAILBOX_STATUS(DSP_TO_MPU)) == 0) {
            REG32(MAILBOX_MESSAGE(DSP_TO_MPU)) = arg;        
        }
        Hwi_restore(key);
    }
    else if (remoteProcId == InterruptDsp_core0ProcId) {
        /* Using mailbox 1 */
        key = Hwi_disable();
        if (REG32(MAILBOX_STATUS(DSP_TO_M3)) == 0) {
            REG32(MAILBOX_MESSAGE(DSP_TO_M3)) = arg;
        }
        Hwi_restore(key);
    }
    else {
        Assert_isTrue(FALSE, ti_sdo_ipc_Ipc_A_internal);
    }
}
示例#3
0
/*!
 *  ======== InterruptM3_intSend ========
 *  Send interrupt to the remote processor
 */
Void InterruptM3_intSend(UInt16 remoteProcId, UArg arg)
{
    Log_print2(Diags_USER1,
        "InterruptM3_intSend: Sending interrupt with payload 0x%x to proc #%d",
        (IArg)arg, (IArg)remoteProcId);
    if (remoteProcId == sysm3ProcId) {
        while(REG32(MAILBOX_FIFOSTATUS(SYSM3_MBX)));
        REG32(MAILBOX_MESSAGE(SYSM3_MBX)) = arg;
    }
    else if (remoteProcId == appm3ProcId) {
        while(REG32(MAILBOX_FIFOSTATUS(APPM3_MBX)));
        /* Write to the mailbox, but this won't trigger an interrupt */
        REG32(MAILBOX_MESSAGE(APPM3_MBX)) = arg;
        /* Actually trigger the interrupt */
        REG16(INTERRUPT_CORE_1) |= 0x1;
    }
    else if (remoteProcId == dspProcId) {
        while(REG32(MAILBOX_FIFOSTATUS(DSP_MBX)));
        REG32(MAILBOX_MESSAGE(DSP_MBX)) = arg;
    }
    else if (remoteProcId == hostProcId) {
        while(REG32(MAILBOX_FIFOSTATUS(HOST_MBX)));
        REG32(MAILBOX_MESSAGE(HOST_MBX)) = arg;
    }
    else {
        /* Should never get here */
        Assert_isTrue(FALSE, NULL);
    }
}
示例#4
0
/*
 *  ======== InterruptHost_intPost ========
 */
Void InterruptHost_intPost(UInt16 srcProcId, IInterrupt_IntInfo *intInfo,
                          UArg arg)
{
    UInt key;

    if (srcProcId == InterruptHost_vpssProcId) { /* VPSS-M3 */
        key = Hwi_disable();
        if (REG32(MAILBOX_STATUS(VPSS_TO_HOST)) == 0) {
            REG32(MAILBOX_MESSAGE(VPSS_TO_HOST)) = arg;
        }
        Hwi_restore(key);
    }
    else if (srcProcId == InterruptHost_videoProcId) { /* VIDEO-M3 */
        key = Hwi_disable();
        if (REG32(MAILBOX_STATUS(VIDEO_TO_HOST)) == 0) {
            REG32(MAILBOX_MESSAGE(VIDEO_TO_HOST)) = arg;
        }
        Hwi_restore(key);
    }
    else if (srcProcId == InterruptHost_dspProcId) {  /* DSP */
        key = Hwi_disable();
        if (REG32(MAILBOX_STATUS(DSP_TO_HOST)) == 0) {
            REG32(MAILBOX_MESSAGE(DSP_TO_HOST)) = arg;
        }
        Hwi_restore(key);
    }
    else { /* EVE */
        key = Hwi_disable();
        if (REG32(EVE_MAILBOX_STATUS(EVE_TO_HOST)) == 0) {
            REG32(EVE_MAILBOX_MESSAGE(EVE_TO_HOST)) = arg;
        }
        Hwi_restore(key);
    }
}
示例#5
0
/*
 *  ======== InterruptHost_intClear ========
 *  Clear interrupt
 */
UInt InterruptHost_intClear(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
    UInt arg;

    if (remoteProcId == InterruptHost_dspProcId) { /* DSP */
        arg = REG32(MAILBOX_MESSAGE(DSP_TO_HOST));
        REG32(MAILBOX_IRQSTATUS_CLR_HOST) = MAILBOX_REG_VAL(DSP_TO_HOST);
    }
    else if (remoteProcId == InterruptHost_videoProcId) { /* VIDEO-M3 */
        arg = REG32(MAILBOX_MESSAGE(VIDEO_TO_HOST));
        REG32(MAILBOX_IRQSTATUS_CLR_HOST) = MAILBOX_REG_VAL(VIDEO_TO_HOST);
    }
    else if (remoteProcId == InterruptHost_vpssProcId) { /* VPSS-M3 */
        arg = REG32(MAILBOX_MESSAGE(VPSS_TO_HOST));
        REG32(MAILBOX_IRQSTATUS_CLR_HOST) = MAILBOX_REG_VAL(VPSS_TO_HOST);
    }
    else { /* EVE */
        arg = REG32(EVE_MAILBOX_MESSAGE(EVE_TO_HOST));  
        REG32(EVE_MAILBOX_IRQSTATUS_CLR_HOST) = MAILBOX_REG_VAL(EVE_TO_HOST);
        
        /* Write to EOI (End Of Interrupt) register */
        REG32(EVE_MAILBOX_EOI_REG) = 0x1;
    }

    return (arg);
}
示例#6
0
/*!
 *  ======== InterruptDucati_intPost ========
 *  Simulate an interrupt from a remote processor
 */
Void InterruptDucati_intPost(UInt16 srcProcId, IInterrupt_IntInfo *intInfo,
                             UArg arg)
{
    UInt key;

    if (srcProcId == InterruptDucati_videoProcId ||
        srcProcId == InterruptDucati_vpssProcId) {
        if (!(BIOS_smpEnabled) && (Core_getId() == 1)) {
            /* VIDEO-M3 to VPSS-M3 */
            REG16(INTERRUPT_VPSS) |= 0x1;
        }
        else {
            /* VPSS-M3 to VIDEO-M3 */
            REG16(INTERRUPT_VIDEO) |= 0x1;
        }
    }
    else if (srcProcId == InterruptDucati_dspProcId) {
        if (!(BIOS_smpEnabled) && (Core_getId() == 1)) {
            /* DSP to VPSS-M3 */
            key = Hwi_disable();
            if (REG32(MAILBOX_STATUS(DSP_TO_VPSS)) == 0) {
                REG32(MAILBOX_MESSAGE(DSP_TO_VPSS)) = arg;
            }
            Hwi_restore(key);
        }
        else {
            /* DSP to VIDEO-M3 */
            key = Hwi_disable();
            if (REG32(MAILBOX_STATUS(DSP_TO_VIDEO)) == 0) {
                REG32(MAILBOX_MESSAGE(DSP_TO_VIDEO)) = arg;
            }
            Hwi_restore(key);
        }
    }
    else { /* HOSTINT */
        if (!(BIOS_smpEnabled) && (Core_getId() == 1)) {
            /* HOST to VPSS-M3 */
            key = Hwi_disable();
            if (REG32(MAILBOX_STATUS(HOST_TO_VPSS)) == 0) {
                REG32(MAILBOX_MESSAGE(HOST_TO_VPSS)) = arg;
            }
            Hwi_restore(key);
        }
        else {
            /* HOST to VIDEO-M3 */
            key = Hwi_disable();
            if (REG32(MAILBOX_STATUS(HOST_TO_VIDEO)) == 0) {
                REG32(MAILBOX_MESSAGE(HOST_TO_VIDEO)) = arg;
            }
            Hwi_restore(key);
        }
    }
}
示例#7
0
/*!
 *  ======== InterruptDucati_intSend ========
 *  Send interrupt to the remote processor
 */
Void InterruptDucati_intSend(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo,
                             UArg arg)
{
    UInt key;

    if (remoteProcId == InterruptDucati_videoProcId ||
        remoteProcId == InterruptDucati_vpssProcId) {
        if (!(BIOS_smpEnabled) && (Core_getId() == 1)) {
            /* VPSS-M3 to VIDEO-M3 */
            REG16(INTERRUPT_VIDEO) |= 0x1;
        }
        else {
            /* VIDEO-M3 to VPSS-M3 */
            REG16(INTERRUPT_VPSS) |= 0x1;
        }
    }
    else if (remoteProcId == InterruptDucati_dspProcId) {
        if (!(BIOS_smpEnabled) && (Core_getId() == 1)) {
            /* VPSS-M3 to DSP */
            key = Hwi_disable();
            if (REG32(MAILBOX_STATUS(VPSS_TO_DSP)) == 0) {
                REG32(MAILBOX_MESSAGE(VPSS_TO_DSP)) = arg;
            }
            Hwi_restore(key);
        }
        else {
            /* VIDEO-M3 to DSP */
            key = Hwi_disable();
            if (REG32(MAILBOX_STATUS(VIDEO_TO_DSP)) == 0) {
                REG32(MAILBOX_MESSAGE(VIDEO_TO_DSP)) = arg;
            }
            Hwi_restore(key);
        }
    }
    else { /* HOSTINT */
        if (!(BIOS_smpEnabled) && (Core_getId() == 1)) {
            /* VPSS-M3 to HOST */
            key = Hwi_disable();
            if (REG32(MAILBOX_STATUS(VPSS_TO_HOST)) == 0) {
                REG32(MAILBOX_MESSAGE(VPSS_TO_HOST)) = arg;
            }
            Hwi_restore(key);
        }
        else {
            /* VIDEO-M3 to HOST */
            key = Hwi_disable();
            if (REG32(MAILBOX_STATUS(VIDEO_TO_HOST)) == 0) {
                REG32(MAILBOX_MESSAGE(VIDEO_TO_HOST)) = arg;
            }
            Hwi_restore(key);
        }
    }
}
示例#8
0
/*
 *  ======== InterruptHost_intSend ========
 *  Send interrupt to the remote processor
 */
Void InterruptHost_intSend(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo,
                          UArg arg)
{
    UInt key;

    /*
     *  Before writing to a mailbox, check whehter it already contains a message
     *  If so, then don't write to the mailbox since we want one and only one
     *  message per interrupt.  Disable interrupts between reading
     *  the MSGSTATUS_X register and writing to the mailbox to protect from
     *  another thread doing an intSend at the same time
     *
     *  Note regarding possible race condition between local 'intSend' and
     *  remote 'intClear':
     *  It is possible that we we read the MAILBOX_MSGSTATUS_X register during
     *  the remote side's intClear.  Therefore, we might choose _not_ to send
     *  write to the mailbox even though the mailbox is about to be cleared a
     *  few cycles later. In this case, the interrupt will be lost.
     *  This is OK, however. intClear should always be called by the Notify
     *  driver _before_ shared memory is read, so the event will be picked up
     *  anyway by the previous interrupt that caused intClear to be called.
     */
    if (remoteProcId == InterruptHost_dspProcId) { /* DSP */
        key = Hwi_disable();
        if (REG32(MAILBOX_STATUS(HOST_TO_DSP)) == 0) {
            REG32(MAILBOX_MESSAGE(HOST_TO_DSP)) = arg;
        }
        Hwi_restore(key);
    }
    else if (remoteProcId == InterruptHost_videoProcId) { /* VIDEO-M3 */
        key = Hwi_disable();
        if (REG32(MAILBOX_STATUS(HOST_TO_VIDEO)) == 0) {
            REG32(MAILBOX_MESSAGE(HOST_TO_VIDEO)) = arg;
        }
        Hwi_restore(key);
    }
    else if (remoteProcId == InterruptHost_vpssProcId) { /* VPSS-M3 */
        key = Hwi_disable();
        if (REG32(MAILBOX_STATUS(HOST_TO_VPSS)) == 0) {
            REG32(MAILBOX_MESSAGE(HOST_TO_VPSS)) = arg;
        }
        Hwi_restore(key);
    }
    else { /* EVE */
        key = Hwi_disable();
        if (REG32(EVE_MAILBOX_STATUS(HOST_TO_EVE)) == 0) {
            REG32(EVE_MAILBOX_MESSAGE(HOST_TO_EVE)) = arg;
        }
        Hwi_restore(key);
    }
}
示例#9
0
/*!
 *  ======== InterruptDucati_intClear ========
 *  Clear interrupt
 */
UInt InterruptDucati_intClear(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
    UInt arg;

    if (remoteProcId == InterruptDucati_videoProcId ||
        remoteProcId == InterruptDucati_vpssProcId) {
        arg = REG32(InterruptDucati_ducatiCtrlBaseAddr);

        /* Look at BIOS's ducati Core id */
        if ((BIOS_smpEnabled) || (Core_getId() == 0)) {
            if ((REG16(INTERRUPT_VIDEO) & 0x1) == 0x1) {
                /* VPSS-M3 to VIDEO-M3 */
                REG16(INTERRUPT_VIDEO) &= ~(0x1);
            }
        }
        else {
            if ((REG16(INTERRUPT_VPSS) & 0x1) == 0x1) {
                /* VIDEO-M3 to VPSS-M3 */
                REG16(INTERRUPT_VPSS) &= ~(0x1);
            }
        }
    }
    else if ((BIOS_smpEnabled) || (Core_getId() == 0)) {
        if (remoteProcId == InterruptDucati_hostProcId) {
            /* HOST to VIDEO-M3 */
            arg = REG32(MAILBOX_MESSAGE(HOST_TO_VIDEO));
            REG32(MAILBOX_IRQSTATUS_CLR_VIDEO) = MAILBOX_REG_VAL(HOST_TO_VIDEO);
        }
        else {
            /* DSP to VIDEO-M3 */
            arg = REG32(MAILBOX_MESSAGE(DSP_TO_VIDEO));
            REG32(MAILBOX_IRQSTATUS_CLR_VIDEO) = MAILBOX_REG_VAL(DSP_TO_VIDEO);
        }
    }
    else { /* M3DSSINT */
        if (remoteProcId == InterruptDucati_hostProcId) {
            /* HOST to VPSS-M3 */
            arg = REG32(MAILBOX_MESSAGE(HOST_TO_VPSS));
            REG32(MAILBOX_IRQSTATUS_CLR_VPSS) = MAILBOX_REG_VAL(HOST_TO_VPSS);
        }
        else {
            /* DSP to VPSS-M3 */
            arg = REG32(MAILBOX_MESSAGE(DSP_TO_VPSS));
            REG32(MAILBOX_IRQSTATUS_CLR_VPSS) = MAILBOX_REG_VAL(DSP_TO_VPSS);
        }
    }

    return (arg);
}
示例#10
0
/*
 *  ======== InterruptEve_intPost ========
 *  Simulate an interrupt from a remote processor
 */
Void InterruptEve_intPost(UInt16 srcProcId, IInterrupt_IntInfo *intInfo,
                            UArg arg)
{
    UInt key;

    if (srcProcId == InterruptEve_hostProcId) {
        /* disable interrupts */
        key = Hwi_disable();

        if (REG32(MAILBOX_STATUS(HOST_TO_EVE)) == 0) {
            /* write the mailbox message to arp32 */
            REG32(MAILBOX_MESSAGE(HOST_TO_EVE)) = arg;
        }

        /* restore interrupts */
        Hwi_restore(key);
    }
    else if ((srcProcId == InterruptEve_videoProcId) ||
        (srcProcId == InterruptEve_vpssProcId)) {
        /* disable interrupts */
        key = Hwi_disable();

        if (REG32(MAILBOX_STATUS(VIDEO_TO_EVE)) == 0) {
            /* write the mailbox message to arp32 */
            REG32(MAILBOX_MESSAGE(VIDEO_TO_EVE)) = arg;
        }

        /* restore interrupts */
        Hwi_restore(key);
    }
    else {
        /* disable interrupts */
        key = Hwi_disable();

        if (REG32(MAILBOX_STATUS(DSP_TO_EVE)) == 0) {
            /* write the mailbox message to arp32 */
            REG32(MAILBOX_MESSAGE(DSP_TO_EVE)) = arg;
        }

        /* restore interrupts */
        Hwi_restore(key);
    }
}
示例#11
0
/*
 *  ======== InterruptEve_intSend ========
 *  Send interrupt to the remote processor
 */
Void InterruptEve_intSend(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo,
                          UArg arg)
{
    UInt key;

    if (remoteProcId == InterruptEve_hostProcId) {
        /* disable interrupts */
        key = Hwi_disable();

        if (REG32(MAILBOX_STATUS(EVE_TO_HOST)) == 0) {
            /* write the mailbox message to host */
            REG32(MAILBOX_MESSAGE(EVE_TO_HOST)) = arg;
        }

        /* restore interrupts */
        Hwi_restore(key);
    }
    else if ((remoteProcId == InterruptEve_videoProcId) ||
        (remoteProcId == InterruptEve_vpssProcId)) {
        /* disable interrupts */
        key = Hwi_disable();

        if (REG32(MAILBOX_STATUS(EVE_TO_VIDEO)) == 0) {
            /* write the mailbox message to video-m3 */
            REG32(MAILBOX_MESSAGE(EVE_TO_VIDEO)) = arg;
        }

        /* restore interrupts */
        Hwi_restore(key);
    }
    else {
        /* disable interrupts */
        key = Hwi_disable();

        if (REG32(MAILBOX_STATUS(EVE_TO_DSP)) == 0) {
            /* write the mailbox message to dsp */
            REG32(MAILBOX_MESSAGE(EVE_TO_DSP)) = arg;
        }

        /* restore interrupts */
        key = Hwi_disable();
    }
}
示例#12
0
/*!
 *  ======== InterruptBenelli_intClear ========
 *  Clear interrupt
 */
UInt InterruptBenelli_intClear(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
    UInt arg;
    UInt16 index;

    index = MBX_TABLE_IDX(remoteProcId, MultiProc_self());
    arg = REG32(MAILBOX_MESSAGE(index));
    REG32(MAILBOX_IRQSTATUS_CLR(index)) = MAILBOX_REG_VAL(SUBMBX_IDX(index));

    return (arg);
}
示例#13
0
/*!
 *  ======== InterruptDsp_intClear ========
 *  Clear interrupt 
 */
UInt InterruptDsp_intClear(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
    UInt arg;
    
    if (remoteProcId == InterruptDsp_hostProcId) {
        /* Mailbox 3 */    
        arg = REG32(MAILBOX_MESSAGE(MPU_TO_DSP)); 
        REG32(MAILBOX_IRQSTATUS_CLR_DSP) = 0x40;
    }
    else if (remoteProcId == InterruptDsp_core0ProcId) {
        /* Mailbox 2 */
        arg = REG32(MAILBOX_MESSAGE(M3_TO_DSP));  
        REG32(MAILBOX_IRQSTATUS_CLR_DSP) = 0x10;            
    }
    else {
        Assert_isTrue(FALSE, ti_sdo_ipc_Ipc_A_internal);
    }    
    
    return (arg);
}
示例#14
0
/*!
 *  ======== InterruptArp32_intClear ========
 *  Clear interrupt
 */
UInt InterruptArp32_intClear(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
    UInt arg;

    /* DSP to ARP32 */
    arg = REG32(MAILBOX_MESSAGE(DSP_TO_ARP32));
    
    /* clear the dsp mailbox */
    REG32(MAILBOX_IRQSTATUS_CLR(MBX_INTR_TO_ARP32)) = MAILBOX_REG_VAL(DSP_TO_ARP32);

    return (arg);
}
示例#15
0
/*!
 *  ======== InterruptM3_intClear ========
 *  Clear interrupt and return payload
 */
UInt InterruptM3_intClear()
{
    UInt arg = InterruptM3_INVALIDPAYLOAD;

    /* First check whether incoming mailbox has a message */
    if (Core_getId() == 0) {
        /* If FIFO is empty, return InterruptM3_INVALIDPAYLOAD */
        if (REG32(MAILBOX_STATUS(SYSM3_MBX)) == 0) {
            return (arg);
        }
        else {
            /* If there is a message, return the argument to the caller */
            arg = REG32(MAILBOX_MESSAGE(SYSM3_MBX));
            REG32(MAILBOX_IRQSTATUS_CLR_M3) = MAILBOX_REG_VAL(SYSM3_MBX);
        }
    }
    else {
        /* Clear the inter-M3 interrupt if necessary */
        if ((REG16(INTERRUPT_CORE_1) & 0x1) == 0x1) {
            REG16(INTERRUPT_CORE_1) &= ~(0x1);
        }

        /* If FIFO is empty, return InterruptM3_INVALIDPAYLOAD */
        if (REG32(MAILBOX_STATUS(APPM3_MBX)) == 0) {
            return (arg);
        }
        else {
            /* If there is a message, return the argument to the caller */
            arg = REG32(MAILBOX_MESSAGE(APPM3_MBX));
            REG32(MAILBOX_IRQSTATUS_CLR_M3) = MAILBOX_REG_VAL(APPM3_MBX);

            if (REG32(MAILBOX_STATUS(APPM3_MBX)) != 0) {
                /* Trigger our own interrupt since another interrupt pending */
                REG16(INTERRUPT_CORE_1) |= 0x1;
            }
        }
    }

    return (arg);
}
示例#16
0
/*!
 *  ======== InterruptDsp_intClear ========
 *  Clear interrupt 
 */
UInt InterruptDsp_intClear(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
    UInt arg;
    
    if (remoteProcId == InterruptDsp_hostProcId) {
        arg = REG32(MAILBOX_MESSAGE(HOST_TO_DSP));  
        REG32(MAILBOX_IRQSTATUS_CLR_DSP) = MAILBOX_REG_VAL(HOST_TO_DSP);
    }
    else if (remoteProcId == InterruptDsp_videoProcId) {
        arg = REG32(MAILBOX_MESSAGE(VIDEO_TO_DSP));  
        REG32(MAILBOX_IRQSTATUS_CLR_DSP) = MAILBOX_REG_VAL(VIDEO_TO_DSP);
    }
    else { /* VPSS-M3 */
        arg = REG32(MAILBOX_MESSAGE(VPSS_TO_DSP));  
        REG32(MAILBOX_IRQSTATUS_CLR_DSP) = MAILBOX_REG_VAL(VPSS_TO_DSP);
    }
    
    /* Write to EOI (End Of Interrupt) register */
    REG32(MAILBOX_EOI_REG) = 0x1;

    return (arg);
}
示例#17
0
/*!
 *  ======== InterruptBenelli_intPost ========
 *  Simulate an interrupt from a remote processor
 */
Void InterruptBenelli_intPost(UInt16 srcProcId, IInterrupt_IntInfo *intInfo,
                             UArg arg)
{
    UInt key;
    UInt16 index;

    index = MBX_TABLE_IDX(srcProcId, MultiProc_self());
    key = Hwi_disable();
    if (REG32(MAILBOX_STATUS(index)) == 0) {
        REG32(MAILBOX_MESSAGE(index)) = arg;
    }
    Hwi_restore(key);
}
示例#18
0
/*
 *  ======== InterruptEve_intClear ========
 *  Clear interrupt
 */
UInt InterruptEve_intClear(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
    UInt arg;

    if (remoteProcId == InterruptEve_hostProcId) { /* HOST */
        arg = REG32(MAILBOX_MESSAGE(HOST_TO_EVE));
        REG32(MAILBOX_IRQSTATUS_CLR_EVE) = MAILBOX_REG_VAL(HOST_TO_EVE);
    }
    else if ((remoteProcId == InterruptEve_videoProcId) || /* VIDEO-M3 */
        (remoteProcId == InterruptEve_vpssProcId)) {
        arg = REG32(MAILBOX_MESSAGE(VIDEO_TO_EVE));
        REG32(MAILBOX_IRQSTATUS_CLR_EVE) = MAILBOX_REG_VAL(VIDEO_TO_EVE);
    }
    else { /* DSP */
        arg = REG32(MAILBOX_MESSAGE(DSP_TO_EVE));
        REG32(MAILBOX_IRQSTATUS_CLR_EVE) = MAILBOX_REG_VAL(DSP_TO_EVE);
    }

    /* Write to EOI (End Of Interrupt) register */
    REG32(MAILBOX_EOI_REG) = 0x1;

    return (arg);
}
示例#19
0
/*!
 *  ======== InterruptDsp_intPost ========
 *  Send interrupt to the remote processor
 */
Void InterruptDsp_intPost(UInt16 srcProcId, IInterrupt_IntInfo *intInfo, 
                          UArg arg)
{
    UInt key;
    
    if (srcProcId == InterruptDsp_hostProcId) {
        key = Hwi_disable();
        if (REG32(MAILBOX_STATUS(MPU_TO_DSP)) == 0) {
            REG32(MAILBOX_MESSAGE(MPU_TO_DSP)) = arg;        
        }
        Hwi_restore(key);
    }
    else if (srcProcId == InterruptDsp_core0ProcId) {
        key = Hwi_disable();
        if (REG32(MAILBOX_STATUS(M3_TO_DSP)) == 0) {
            REG32(MAILBOX_MESSAGE(M3_TO_DSP)) = arg;
        }
        Hwi_restore(key);
    }
    else {
        Assert_isTrue(FALSE, ti_sdo_ipc_Ipc_A_internal);
    }
}
示例#20
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/*!
 *  ======== InterruptDsp_intClear ========
 *  Clear interrupt 
 */
UInt InterruptDsp_intClear(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
    UInt arg;
    
    arg = REG32(MAILBOX_MESSAGE(ARP32_TO_DSP));
    
    /* clear the dsp mailbox */
    REG32(MAILBOX_IRQSTATUS_CLR(MBX_INTR_TO_DSP)) = MAILBOX_REG_VAL(ARP32_TO_DSP);
    
    /* Write to EOI (End Of Interrupt) register */
    REG32(MAILBOX_EOI_REG) = 0x1;

    return (arg);
}
示例#21
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/*!
 *  ======== InterruptDsp_intClear ========
 *  Clear interrupt 
 */
UInt InterruptDsp_intClear(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
    UInt arg;
    UInt16 index;
    
    index = MBX_TABLE_IDX(remoteProcId, MultiProc_self());
    
    arg = REG32(MAILBOX_MESSAGE(index));
    REG32(MAILBOX_IRQSTATUS_CLR_DSP(index)) = MAILBOX_REG_VAL(SUBMBX_IDX(index));
    
    /* Write to EOI (End Of Interrupt) register */
    REG32(MAILBOX_EOI_REG(index)) = 0x1;

    return (arg);
}
示例#22
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/*!
 *  ======== InterruptArp32_intSend ========
 *  Send interrupt to the remote processor
 */
Void InterruptArp32_intSend(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo,
                             UArg arg)
{
    UInt key;

    /* disable interrupts */
    key = Hwi_disable();
    
    if (REG32(MAILBOX_STATUS(ARP32_TO_DSP)) == 0) {
        /* write the mailbox message to dsp */
        REG32(MAILBOX_MESSAGE(ARP32_TO_DSP)) = arg;
    }
    
    /* restore interrupts */
    Hwi_restore(key);
}
示例#23
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/*!
 *  ======== InterruptArp32_intPost ========
 *  Simulate an interrupt from a remote processor
 */
Void InterruptArp32_intPost(UInt16 srcProcId, IInterrupt_IntInfo *intInfo,
                             UArg arg)
{
    UInt key;

    /* disable interrupts */
    key = Hwi_disable();

    if (REG32(MAILBOX_STATUS(DSP_TO_ARP32)) == 0) {
        /* write the mailbox message to arp32 */
        REG32(MAILBOX_MESSAGE(DSP_TO_ARP32)) = arg;
    }
    
    /* restore interrupts */
    Hwi_restore(key);
}
示例#24
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/*!
 *  ======== InterruptIpu_intClear ========
 *  Clear interrupt and return payload
 */
UInt InterruptIpu_intClear()
{
	UInt arg = INVALIDPAYLOAD;

	/* If FIFO is empty, return INVALIDPAYLOAD */
	if (REG32(MAILBOX_STATUS(HOST_TO_SYSM3_MBX)) == 0) {
		return (arg);
	}
	else {
		/* If there is a message, return the argument to the caller */
		arg = REG32(MAILBOX_MESSAGE(HOST_TO_SYSM3_MBX));
		REG32(MAILBOX_IRQSTATUS_CLR_M3) =
				MAILBOX_REG_VAL(HOST_TO_SYSM3_MBX);
	}

	return (arg);
}
示例#25
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/*!
 *  ======== InterruptArp32_intPost ========
 *  Simulate an interrupt from a remote processor
 */
Void InterruptArp32_intPost(UInt16 srcProcId, IInterrupt_IntInfo *intInfo,
                             UArg arg)
{
    UInt key;
    UInt16 index;

    index = MBX_TABLE_IDX(srcProcId, MultiProc_self());

    /* disable interrupts */
    key = Hwi_disable();

    if (REG32(MAILBOX_STATUS(index)) == 0) {
        /* write the mailbox message to arp32 */
        REG32(MAILBOX_MESSAGE(index)) = arg;
    }
    
    /* restore interrupts */
    Hwi_restore(key);
}
};

/*
 * MAILBOX 0: ARM -> DSP,
 * MAILBOX 1: ARM <- DSP.
 * MAILBOX 2: ARM -> IVA,
 * MAILBOX 3: ARM <- IVA.
 * MAILBOX 4: ARM -> wrigley c55,
 * MAILBOX 5: ARM <- wrigley c55,
 */

/* FIXME: the following structs should be filled automatically by the user id */
/* DSP */
static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
	.tx_fifo = {
		.msg		= MAILBOX_MESSAGE(0),
		.fifo_stat	= MAILBOX_FIFOSTATUS(0),
	},
	.rx_fifo = {
		.msg		= MAILBOX_MESSAGE(1),
		.msg_stat	= MAILBOX_MSGSTATUS(1),
	},
	.irqenable	= MAILBOX_IRQENABLE(0),
	.irqstatus	= MAILBOX_IRQSTATUS(0),
	.notfull_bit	= MAILBOX_IRQ_NOTFULL(0),
	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(1),
	.irqdisable	= MAILBOX_IRQENABLE(0),
};


示例#27
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/*!
 *  ======== InterruptIpu_intSend ========
 *  Send interrupt to the remote processor
 */
Void InterruptIpu_intSend(UInt arg)
{
	while(REG32(MAILBOX_FIFOSTATUS(M3_TO_HOST_MBX)));
	REG32(MAILBOX_MESSAGE(M3_TO_HOST_MBX)) = arg;
}