void C_DM9000::DeviceEnableReceive(void)
{
// RX enable RXCR<0>
if(m_szCurrentSettings[SID_OP_MODE] & MAKE_MASK(0)) return;
m_szCurrentSettings[SID_OP_MODE] |= MAKE_MASK(0);
DeviceWritePort(DM9_RXCR,m_szCurrentSettings[SID_OP_MODE]);
}
F_TYPE
F_ENTRY_NAME( F_TYPE x )
{
EXCEPTION_RECORD_DECLARATION
B_TYPE fm, z, w, t;
B_UNION stack_tmp_u;
F_UNION stack_tmp_v;
U_WORD status_word;
WORD m, i, j;
# if !COMPATIBILITY_MODE
WORD func_error_word ;
# endif
/*
** Weed out: near overflow and underflow cases; NaN's, Inf's and
** denorms; arguments that would underflow during polynomial
** evaluation.
**
** The product x*(1/ln2) is on the critical path of this routine.
** Because the code is structured with a branch prior to the
** multiplication, some compilers fail to schedule the load of the
** constant 1/ln2 early enough to avoid delaying the reduced argument
** computation. To avoid this delay, we preload (1/ln2).
*/
stack_tmp_v.f = x;
i = stack_tmp_v.F_SIGNED_HI_WORD;
m = i & MAKE_MASK(F_SIGN_BIT_POS, 0);
NOT_EXP2( t = EXP_EXP10_SELECT(RECIP_LN2, LN10_OV_LN2); )
if (((U_WORD) m - EXP_LO_CHECK) >= EXP_HI_CHECK)
U16 C_DM9000::DeviceWriteEeprom(
U32 uWordAddress,
U16 uValue)
{
// assign the register offset
DeviceWritePort(DM9_EPADDR,uWordAddress);
// put data
DeviceWritePort(DM9_EPLOW, LOW_BYTE(uValue));
DeviceWritePort(DM9_EPHIGH,HIGH_BYTE(uValue));
// issue EEPROM write enable<4> and write command<1>
DeviceWritePort(DM9_EPCNTL,MAKE_MASK2(4,1));
// wait until status bit<0> cleared
DevicePolling(DM9_EPCNTL,MAKE_MASK(0),0x00);
// stop command
DeviceWritePort(DM9_EPCNTL,0);
// extra delay
NdisStallExecution(1000);
return uValue;
}
static void
copy_bits(u_int8_t* src, /* Base pointer to source. */
size_t soffs, /* Bit offset for source relative to src. */
int sdir, /* Direction: 1 (forward) or -1 (backward). */
u_int8_t* dst, /* Base pointer to destination. */
size_t doffs, /* Bit offset for destination relative to dst. */
int ddir, /* Direction: 1 (forward) or -1 (backward). */
size_t n) /* Number of bits to copy. */
{
u_int32_t lmask;
u_int32_t rmask;
u_int32_t count;
u_int32_t deoffs;
if (n == 0) {
return;
}
src += sdir*BYTE_OFFSET(soffs);
dst += ddir*BYTE_OFFSET(doffs);
soffs = BIT_OFFSET(soffs);
doffs = BIT_OFFSET(doffs);
deoffs = BIT_OFFSET(doffs+n);
lmask = (doffs) ? MAKE_MASK(8-doffs) : 0;
rmask = (deoffs) ? (MAKE_MASK(deoffs)<<(8-deoffs)) : 0;
/*
* Take care of the case that all bits are in the same byte.
*/
if (doffs+n < 8) { /* All bits are in the same byte */
lmask = (lmask & rmask) ? (lmask & rmask) : (lmask | rmask);
if (soffs == doffs) {
*dst = MASK_BITS(*src,*dst,lmask);
} else if (soffs > doffs) {
u_int32_t bits = (*src << (soffs-doffs));
if (soffs+n > 8) {
src += sdir;
bits |= (*src >> (8-(soffs-doffs)));
}
void C_DM9000::DeviceStart(void)
{
#ifdef IMPL_FLOW_CONTROL
U32 val;
// set PHY supports flow control
DeviceWritePhy(0, 4, (DeviceReadPhy(0,4)|(1<<10)));
// check full-duplex mode or not<3>
val = DeviceReadPort(DM9_NCR);
if( val & MAKE_MASK(3))
{
/* full duplex mode */
val = DeviceReadPort(DM9_PAUSETH);
DeviceWritePort(DM9_PAUSETH,(U8)val);
// enable flow control<0>
// enable pause packet<5>
DeviceWritePort(DM9_FLOW,MAKE_MASK2(5,0));
}
else
{
/* non full duplex mode */
val = DeviceReadPort(DM9_BACKTH);
DeviceWritePort(DM9_BACKTH,(U8)val);
// enable back pressure<half dumplex mode)<4,3>
DeviceWritePort(DM9_FLOW,MAKE_MASK2(4,3));
}
#endif
// enable interrupt
DeviceEnableInterrupt();
DeviceWritePort(DM9_RXCR,m_szCurrentSettings[SID_OP_MODE]);
}
int C_DM9000::DeviceSend(
PCQUEUE_GEN_HEADER pObject)
{
PCQUEUE_GEN_HEADER pcurr;
if(pObject) m_TQStandby.Enqueue(pObject);
/* increment counter */
m_nTxPendings++;
/* get first pkt in queue */
m_TQWaiting.Enqueue(pcurr=m_TQStandby.Dequeue());
/* fill data */
DeviceWriteString((PU8)CQueueGetUserPointer(pcurr),pcurr->nLength);
DeviceWritePort(DM9_TXLENH,HIGH_BYTE(pcurr->nLength));
DeviceWritePort(DM9_TXLENL,LOW_BYTE(pcurr->nLength));
// TXCR<0>, issue TX request
DeviceWritePort(DM9_TXCR, MAKE_MASK(0));
return 0;
}
int v_initialize (void)
{
sdl_init();
setup_hex( hex_size );
{
int i;
for (i=0; i<256; i++) {
cols[i].r = i*16;
cols[i].g = i*16;
cols[i].b = i*16;
cols[i].unused = 255;
}
}
MAKE_COLOR(TEXT_INDEX , 64, 64, 64, 255);
MAKE_COLOR(STATUS_INDEX , 255, 255, 255, 255);
MAKE_COLOR(ROCK_INDEX , 128, 128, 128, 255);
MAKE_COLOR(ROCK2_INDEX , 64, 64, 128, 255);
MAKE_COLOR(EMPTY_INDEX , 240, 240, 240, 255);
MAKE_COLOR(FRAME_INDEX , 200, 200, 200, 255);
MAKE_COLOR(HEAD_INDEX , 0, 0, 0, 255);
MAKE_COLOR(RED_INDEX , 240, 0, 0, 255);
MAKE_COLOR(BLACK_INDEX , 0, 128, 0, 255);
MAKE_COLOR(RED_HOME_INDEX , 200, 0, 0, 128);
MAKE_COLOR(BLACK_HOME_INDEX , 0, 200, 0, 128);
MAKE_COLOR(RED_ANT_INDEX , 240, 0, 0, 255);
MAKE_COLOR(BLACK_ANT_INDEX , 0, 160, 0, 255);
MAKE_COLOR(RED_FOOD_INDEX , 240, 128, 128, 255);
MAKE_COLOR(BLACK_FOOD_INDEX , 128, 200, 128, 255);
MAKE_COLOR(S_BACK_INDEX , 240, 240, 240, 255);
MAKE_COLOR(S_DIR_INDEX , 0, 0, 0, 255);
MAKE_COLOR(S_BIT3_INDEX , 255, 200, 200, 255);
MAKE_COLOR(S_BIT4_INDEX , 200, 255, 200, 255);
MAKE_COLOR(S_BIT5_INDEX , 200, 200, 255, 255);
MAKE_MASK( 4, 0, MASK_RED, 0, 0x3, 32);
MAKE_MASK( 4, 1, MASK_RED, 2, 0x3, 32);
MAKE_MASK( 4, 2, MASK_RED, 4, 0x3, 32);
MAKE_MASK( 4, 3, MASK_BLACK, 0, 0x3, 32);
MAKE_MASK( 4, 4, MASK_BLACK, 2, 0x3, 32);
MAKE_MASK( 4, 5, MASK_BLACK, 4, 0x3, 32);
MAKE_MASK( 5, 0, MASK_RED, 0, 0x1, 64);
MAKE_MASK( 5, 1, MASK_RED, 1, 0x1, 64);
MAKE_MASK( 5, 2, MASK_RED, 2, 0x1, 64);
MAKE_MASK( 5, 3, MASK_RED, 3, 0x1, 64);
MAKE_MASK( 5, 4, MASK_RED, 4, 0x1, 64);
MAKE_MASK( 5, 5, MASK_RED, 5, 0x1, 64);
MAKE_MASK( 6, 0, MASK_BLACK, 0, 0x1, 64);
MAKE_MASK( 6, 1, MASK_BLACK, 1, 0x1, 64);
MAKE_MASK( 6, 2, MASK_BLACK, 2, 0x1, 64);
MAKE_MASK( 6, 3, MASK_BLACK, 3, 0x1, 64);
MAKE_MASK( 6, 4, MASK_BLACK, 4, 0x1, 64);
MAKE_MASK( 6, 5, MASK_BLACK, 5, 0x1, 64);
sdl_setcols(&cols[64], 64, 16);
return 0;
}
int C_DM9000::DeviceOnSetupFilter(
U32 uFilter)
{
int n;
U8 sz[8];
U32 hashval;
U32 newmode;
// save old op mode
newmode = m_szCurrentSettings[SID_OP_MODE];
// clear filter related bits,
// pass all multicast<3> and promiscuous<1>
newmode &= ~MAKE_MASK2(3,1);
// zero input means one reset request
if(!(m_szCurrentSettings[SID_GEN_CURRENT_PACKET_FILTER]=uFilter))
{
/* 1. set unicast */
// retrive node address
DeviceMacAddress(&sz[0]);
// set node address
for(n=0;n<ETH_ADDRESS_LENGTH;n++)
DeviceWritePort(DM9_PAR0+n,(U32)sz[n]);
/* 2. clear multicast list and count */
m_nMulticasts = 0;
memset((void*)&m_szMulticastList,0,sizeof(m_szMulticastList));
/* 3. clear hash table */
// clear hash table
memset((void*)(&sz[0]),0,sizeof(sz));
for(n=0;n<sizeof(sz);n++)
DeviceWritePort(DM9_MAR0+n,(U32)sz[n]);
return uFilter;
}
// if promiscuous mode<1> is requested,
// just set this bit and return
if( (uFilter & NDIS_PACKET_TYPE_PROMISCUOUS) )
{
// add promiscuous<1>
newmode |= MAKE_MASK(1);
DeviceWritePort(DM9_RXCR,m_szCurrentSettings[SID_OP_MODE]=newmode);
return uFilter;
}
// if pass all multicast<3> is requested,
if(uFilter & NDIS_PACKET_TYPE_ALL_MULTICAST) newmode |= MAKE_MASK(3);
// prepare new hash table
memset((void*)(&sz[0]),0,sizeof(sz));
// if broadcast, its hash value is known as 63.
if(uFilter & NDIS_PACKET_TYPE_BROADCAST) sz[7] |= 0x80;
if(uFilter & NDIS_PACKET_TYPE_MULTICAST)
for(n=0;n<m_nMulticasts;n++)
{
hashval = DeviceCalculateCRC32(
&m_szMulticastList[n][0],ETH_ADDRESS_LENGTH,FALSE) & 0x3f;
sz[hashval/8] |= 1 << (hashval%8);
} // of calculate hash table
// submit the new hash table
for(n=0;n<sizeof(sz);n++)
DeviceWritePort(DM9_MAR0+n,(U32)sz[n]);
DeviceWritePort(DM9_RXCR,m_szCurrentSettings[SID_OP_MODE]=newmode);
return uFilter;
}
void C_DM9000::EDeviceInitialize(
int nResetCounts)
{
U32 val;
// reset member varialbes
m_uLastAddressPort = (U32)-1;
DeviceWritePort(0x1f, 0x00);
NdisStallExecution(20);
// software reset the device
DeviceWritePort(DM9_NCR, 0x03);
NdisStallExecution(20);
DeviceWritePort(DM9_NCR, 0x03);
NdisStallExecution(20);
//DeviceWritePort(DM9_NCR, 0x00);
// read the io orgnization
// ISR<7:6> == x1, dword
// ISR<7:6> == 0x, word
// ISR<7:6> == 10, byte mode
val = DeviceReadPort(DM9_ISR);
if(val & MAKE_MASK(6))
{
m_nIoMode = DWORD_MODE;
m_nIoMaxPad = 3;
}
else if(!(val & MAKE_MASK(7)))
{
m_nIoMode = WORD_MODE;
m_nIoMaxPad = 1;
}
else
{
m_nIoMode = BYTE_MODE;
m_nIoMaxPad = 0;
}
// activate internal phy
// select GPIO 0<0>, set it to output
DeviceWritePort(DM9_GPCR, (1<<0));
// output zero to activate internal phy
DeviceWritePort(DM9_GPR, 0x00);
// clear TX status
DeviceWritePort(DM9_NSR, 0x00);
// Enable memory chain
DeviceWritePort(DM9_IMR, (1<<7));
#ifdef IMPL_STORE_AND_INDICATION
if(nResetCounts) return;
/* init rx buffers */
U32 m,uaddr;
if(!(uaddr = (U32)malloc(sizeof(DATA_BLOCK)*
(m=m_szConfigures[CID_RXBUFFER_NUMBER]*2))))
THROW((ERR_STRING("Insufficient memory")));
for(;m--;uaddr+=sizeof(DATA_BLOCK))
m_RQueue.Enqueue((PCQUEUE_GEN_HEADER)uaddr);
/* set indication timer */
DeviceInitializeTimer();
#endif
// v3.2.9
m_nMaxTxPending = (DeviceReadPort(DM9_CHIPREV) >= 0x10)?2:1;
m_nTxPendings = 0;
}
