level = i; level = mali_freq_num-level - 1; } } return level; } unsigned int get_mali_max_level(void) { return mali_plat_data.dvfs_table_size - 1; } static struct resource mali_gpu_resources[] = { MALI_GPU_RESOURCES_MALI450_MP2_PMU(IO_MALI_APB_PHY_BASE, INT_MALI_GP, INT_MALI_GP_MMU, INT_MALI_PP0, INT_MALI_PP0_MMU, INT_MALI_PP1, INT_MALI_PP1_MMU, INT_MALI_PP) }; static void set_limit_mali_freq(u32 idx) { if (mali_plat_data.limit_on == 0) return; if (idx > mali_plat_data.turbo_clock || idx < mali_plat_data.scale_info.minclk) return; mali_plat_data.scale_info.maxclk= idx; revise_mali_rt(); } static u32 get_limit_mali_freq(void)
.def_clock = CFG_CLOCK, /* gpu clock used most of time.*/ .cfg_clock = CFG_CLOCK, /* max gpu clock. */ .cfg_min_clock = CFG_MIN_CLOCK, .clk = mali_dvfs_clk, /* clock source table. */ .clk_sample = mali_dvfs_clk_sample, /* freqency table for show. */ .clk_len = sizeof(mali_dvfs_clk) / sizeof(mali_dvfs_clk[0]), .have_switch = 0, }; #define MALI_USER_PP0 AM_IRQ4(31) static struct resource mali_gpu_resources[] = { MALI_GPU_RESOURCES_MALI450_MP2_PMU(0xC9140000, INT_MALI_GP, INT_MALI_GP_MMU, MALI_USER_PP0, INT_MALI_PP_MMU, INT_MALI_PP1, INT_MALI_PP_MMU1, INT_MALI_PP) }; int mali_meson_init_start(struct platform_device* ptr_plt_dev) { ptr_plt_dev->num_resources = ARRAY_SIZE(mali_gpu_resources); ptr_plt_dev->resource = mali_gpu_resources; return mali_clock_init(&mali_plat_data); } int mali_meson_init_finish(struct platform_device* ptr_plt_dev) { return 0; }