示例#1
0
inline uint16_t enc28_SPISend(uint16_t ui16_rw) {
  uint32_t ui32_rx_val;
  MAP_SSIDataPut(ui32_SSIx, ui16_rw);
  while(MAP_SSIBusy(SSI0_BASE));
  MAP_SSIDataGet(ui32_SSIx, &ui32_rx_val);
  return (uint16_t)ui32_rx_val;
}
示例#2
0
文件: spi.c 项目: cydvicious/rone
/*
 * @brief Deselects all select/latch pins
 * Waits till all transfers are finished
 * @return if their is a error return FALSE else ture
 */
boolean SPIDeselectISR(void) {
    // wait until the last transfer is finished
    volatile uint16 i = 0;

    while (MAP_SSIBusy(SSI0_BASE)) {
        i++;
        if (i > SPI_MAX_XFER_IRQ_DELAY) {
            SPIBusError_SPIDeselectISR = TRUE;
            return FALSE;
        }
    }

    i = i + 1;
#if (defined(RONE_V12) || defined(RONE_V9))
    //set output enable low, which pulls all spi select lines high
    MAP_GPIOPinWrite(SPI_ENABLE_PORT, SPI_ENABLE_PIN, 0);
    MAP_GPIOPinWrite(SPI_SELECT_PORT, SPI_SELECT_PINS, NULL_SELECT_PINS);
#endif
    return TRUE;
}
示例#3
0
文件: spi.c 项目: cydvicious/rone
/*
 * @brief Cancels all selections. Then immediately sends a byte of 0xFF.
 *
 * Makes all SPI devices inactive. Then immediately sends a byte of 0xFF.
 * @returns void
 */
void SPIDeselectSynchronous(void) {
    // do the actual deselect
    SPIDeselectISR();

    //Send a 0xFF byte
    //Load up the data and send it
    uint32 rcvdat;
    MAP_SSIDataPut(SSI0_BASE, 0xFF); /* Write the data to the tx fifo */
    MAP_SSIDataGet(SSI0_BASE, &rcvdat); /* flush data read during the write */

    // wait until the last transfer is finished
    volatile uint16 i = 0;

    while (MAP_SSIBusy(SSI0_BASE)) {
        i++;
        if (i > SPI_MAX_XFER_IRQ_DELAY) {
            return;
        }
    }
}