static int mdio_write(int argc, char *argv[]){ int rv; int c; rtk_uint32 preamble_len = 0; rtk_uint32 phy_id = 0; rtk_uint32 register_id = 0; rtk_uint32 data = 0; static const char * shortopts = "l:p:r:d:"; static const struct option longopts[] = { {"len", required_argument, NULL, 'l'}, {"pid", required_argument, NULL, 'p'}, {"rid", required_argument, NULL, 'r'}, {"data", required_argument, NULL, 'd'}, {NULL, 0, NULL, 0} }; while((c = getopt_long(argc,argv,shortopts,longopts,NULL)) != -1){ switch(c){ case 'l': preamble_len = strtol(optarg, NULL, 0); break; case 'p': phy_id = strtol(optarg, NULL, 0); break; case 'r': register_id = strtol(optarg, NULL, 0); break; case 'd': data = strtol(optarg, NULL, 0); break; default: break; } } rv = MDC_MDIO_WRITE( preamble_len, phy_id, register_id, data); if(rv){ printf("mdio write error!"); return 1; } return 0; }
int smi_write(u32 addr, u32 data) { unsigned long flags; spin_lock_irqsave(&g_mdio_lock, flags); /* We enable mdio gpio purpose register, and disable it when exit. */ gpio_set_mdio_unlocked(1); /* Write Start command to register 29 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, g_phy_id, MDC_MDIO_START_REG, MDC_MDIO_START_OP); /* Write address control code to register 31 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, g_phy_id, MDC_MDIO_CTRL0_REG, MDC_MDIO_ADDR_OP); /* Write Start command to register 29 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, g_phy_id, MDC_MDIO_START_REG, MDC_MDIO_START_OP); /* Write address to register 23 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, g_phy_id, MDC_MDIO_ADDRESS_REG, addr); /* Write Start command to register 29 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, g_phy_id, MDC_MDIO_START_REG, MDC_MDIO_START_OP); /* Write data to register 24 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, g_phy_id, MDC_MDIO_DATA_WRITE_REG, data); /* Write Start command to register 29 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, g_phy_id, MDC_MDIO_START_REG, MDC_MDIO_START_OP); /* Write data control code to register 21 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, g_phy_id, MDC_MDIO_CTRL1_REG, MDC_MDIO_WRITE_OP); gpio_set_mdio_unlocked(0); spin_unlock_irqrestore(&g_mdio_lock, flags); return RT_ERR_OK; }
int32 smi_write(uint32 mAddrs, uint32 rData) { #if MDC_MDIO_OPERATION /* Write address control code to register 13 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_CTRL_REG, MDC_MDIO_ADDR_OP); /* Write address to register 14 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_DATA_REG, mAddrs); /* Write data control code to register 13 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_CTRL_REG, MDC_MDIO_DATA_OP); /* Write data to register 14 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_DATA_REG, rData); return SUCCESS; #else int8 con; uint32 ACK; uint32 ret = SUCCESS; /*Disable CPU interrupt to ensure that the SMI operation is atomic. The API is based on RTL865X, rewrite the API if porting to other platform.*/ rtlglue_drvMutexLock(); _smi_start(); /* Start SMI */ _smi_writeBit(0x0a, 4); /* CTRL code: 4'b1010 */ _smi_writeBit(0x4, 3); /* CTRL code: 3'b100 */ _smi_writeBit(0x0, 1); /* 0: issue WRITE command */ con = 0; do { con++; _smi_readBit(1, &ACK); /* ACK for issuing WRITE command*/ } while ((ACK != 0) && (con < ack_timer)); if (ACK != 0) ret = FAILED; _smi_writeBit((mAddrs&0xff), 8); /* Set reg_addr[7:0] */ con = 0; do { con++; _smi_readBit(1, &ACK); /* ACK for setting reg_addr[7:0] */ } while ((ACK != 0) && (con < ack_timer)); if (ACK != 0) ret = FAILED; _smi_writeBit((mAddrs>>8), 8); /* Set reg_addr[15:8] */ con = 0; do { con++; _smi_readBit(1, &ACK); /* ACK for setting reg_addr[15:8] */ } while ((ACK != 0) && (con < ack_timer)); if (ACK != 0) ret = FAILED; _smi_writeBit(rData&0xff, 8); /* Write Data [7:0] out */ con = 0; do { con++; _smi_readBit(1, &ACK); /* ACK for writting data [7:0] */ } while ((ACK != 0) && (con < ack_timer)); if (ACK != 0) ret = FAILED; _smi_writeBit(rData>>8, 8); /* Write Data [15:8] out */ con = 0; do { con++; _smi_readBit(1, &ACK); /* ACK for writting data [15:8] */ } while ((ACK != 0) && (con < ack_timer)); if (ACK != 0) ret = FAILED; _smi_stop(); rtlglue_drvMutexUnlock();/*enable CPU interrupt*/ return ret; #endif /* end of #if MDC_MDIO_OPEARTION */ }
int32 smi_read(uint32 mAddrs, uint32 *rData) { #if MDC_MDIO_OPERATION /* Write address control code to register 13 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_CTRL_REG, MDC_MDIO_ADDR_OP); /* Write address to register 14 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_DATA_REG, mAddrs); /* Write data control code to register 13 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_CTRL_REG, MDC_MDIO_DATA_OP); /* Read data from register 14 */ MDC_MDIO_READ(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_DATA_REG, rData); return SUCCESS; #else uint32 rawData=0, ACK; uint8 con; uint32 ret = SUCCESS; /* if ((mAddrs > max_register) || (rData == NULL)) return FAILED; */ /*Disable CPU interrupt to ensure that the SMI operation is atomic. The API is based on RTL865X, rewrite the API if porting to other platform.*/ rtlglue_drvMutexLock(); _smi_start(); /* Start SMI */ _smi_writeBit(0x0a, 4); /* CTRL code: 4'b1010 */ _smi_writeBit(0x4, 3); /* CTRL code: 3'b100 */ _smi_writeBit(0x1, 1); /* 1: issue READ command */ con = 0; do { con++; _smi_readBit(1, &ACK); /* ACK for issuing READ command*/ } while ((ACK != 0) && (con < ack_timer)); if (ACK != 0) ret = FAILED; _smi_writeBit((mAddrs&0xff), 8); /* Set reg_addr[7:0] */ con = 0; do { con++; _smi_readBit(1, &ACK); /* ACK for setting reg_addr[7:0] */ } while ((ACK != 0) && (con < ack_timer)); if (ACK != 0) ret = FAILED; _smi_writeBit((mAddrs>>8), 8); /* Set reg_addr[15:8] */ con = 0; do { con++; _smi_readBit(1, &ACK); /* ACK by RTL8369 */ } while ((ACK != 0) && (con < ack_timer)); if (ACK != 0) ret = FAILED; _smi_readBit(8, &rawData); /* Read DATA [7:0] */ *rData = rawData&0xff; _smi_writeBit(0x00, 1); /* ACK by CPU */ _smi_readBit(8, &rawData); /* Read DATA [15: 8] */ _smi_writeBit(0x01, 1); /* ACK by CPU */ *rData |= (rawData<<8); _smi_stop(); rtlglue_drvMutexUnlock();/*enable CPU interrupt*/ return ret; #endif /* end of #if MDC_MDIO_OPEARTION */ }
rtk_int32 smi_write(rtk_uint32 mAddrs, rtk_uint32 rData) { #if defined(MDC_MDIO_OPERATION) /* Write Start command to register 29 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_START_REG, MDC_MDIO_START_OP); /* Write address control code to register 31 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_CTRL0_REG, MDC_MDIO_ADDR_OP); /* Write Start command to register 29 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_START_REG, MDC_MDIO_START_OP); /* Write address to register 23 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_ADDRESS_REG, mAddrs); /* Write Start command to register 29 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_START_REG, MDC_MDIO_START_OP); /* Write data to register 24 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_DATA_WRITE_REG, rData); /* Write Start command to register 29 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_START_REG, MDC_MDIO_START_OP); /* Write data control code to register 21 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_CTRL1_REG, MDC_MDIO_WRITE_OP); return RT_ERR_OK; #elif defined(SPI_OPERATION) /* Write 8 bits WRITE OP_CODE */ SPI_WRITE(SPI_WRITE_OP, SPI_WRITE_OP_LEN); /* Write 16 bits register address */ SPI_WRITE(mAddrs, SPI_REG_LEN); /* Write 16 bits data */ SPI_WRITE(rData, SPI_DATA_LEN); #else /* if ((mAddrs > 0x018A) || (rData > 0xFFFF)) return RT_ERR_FAILED; */ rtk_int8 con; rtk_uint32 ACK; rtk_uint32 ret = RT_ERR_OK; /*Disable CPU interrupt to ensure that the SMI operation is atomic. The API is based on RTL865X, rewrite the API if porting to other platform.*/ rtlglue_drvMutexLock(); _smi_start(); /* Start SMI */ _smi_writeBit(0x0b, 4); /* CTRL code: 4'b1011 for RTL8370*/ _smi_writeBit(0x4, 3); /* CTRL code: 3'b100 */ _smi_writeBit(0x0, 1); /* 0: issue WRITE command */ con = 0; do { con++; _smi_readBit(1, &ACK); /* ACK for issuing WRITE command*/ } while ((ACK != 0) && (con < ack_timer)); if (ACK != 0) ret = RT_ERR_FAILED; _smi_writeBit((mAddrs&0xff), 8); /* Set reg_addr[7:0] */ con = 0; do { con++; _smi_readBit(1, &ACK); /* ACK for setting reg_addr[7:0] */ } while ((ACK != 0) && (con < ack_timer)); if (ACK != 0) ret = RT_ERR_FAILED; _smi_writeBit((mAddrs>>8), 8); /* Set reg_addr[15:8] */ con = 0; do { con++; _smi_readBit(1, &ACK); /* ACK for setting reg_addr[15:8] */ } while ((ACK != 0) && (con < ack_timer)); if (ACK != 0) ret = RT_ERR_FAILED; _smi_writeBit(rData&0xff, 8); /* Write Data [7:0] out */ con = 0; do { con++; _smi_readBit(1, &ACK); /* ACK for writting data [7:0] */ } while ((ACK != 0) && (con < ack_timer)); if (ACK != 0) ret = RT_ERR_FAILED; _smi_writeBit(rData>>8, 8); /* Write Data [15:8] out */ con = 0; do { con++; _smi_readBit(1, &ACK); /* ACK for writting data [15:8] */ } while ((ACK != 0) && (con < ack_timer)); if (ACK != 0) ret = RT_ERR_FAILED; _smi_stop(); rtlglue_drvMutexUnlock();/*enable CPU interrupt*/ return ret; #endif /* end of #if defined(MDC_MDIO_OPERATION) */ }
rtk_int32 smi_read(rtk_uint32 mAddrs, rtk_uint32 *rData) { #if defined(MDC_MDIO_OPERATION) /* Write Start command to register 29 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_START_REG, MDC_MDIO_START_OP); /* Write address control code to register 31 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_CTRL0_REG, MDC_MDIO_ADDR_OP); /* Write Start command to register 29 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_START_REG, MDC_MDIO_START_OP); /* Write address to register 23 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_ADDRESS_REG, mAddrs); /* Write Start command to register 29 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_START_REG, MDC_MDIO_START_OP); /* Write read control code to register 21 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_CTRL1_REG, MDC_MDIO_READ_OP); /* Write Start command to register 29 */ MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_START_REG, MDC_MDIO_START_OP); /* Read data from register 25 */ MDC_MDIO_READ(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_DATA_READ_REG, rData); return RT_ERR_OK; #elif defined(SPI_OPERATION) /* Write 8 bits READ OP_CODE */ SPI_WRITE(SPI_READ_OP, SPI_READ_OP_LEN); /* Write 16 bits register address */ SPI_WRITE(mAddrs, SPI_REG_LEN); /* Read 16 bits data */ SPI_READ(rData, SPI_DATA_LEN); #else rtk_uint32 rawData=0, ACK; rtk_uint8 con; rtk_uint32 ret = RT_ERR_OK; /*Disable CPU interrupt to ensure that the SMI operation is atomic. The API is based on RTL865X, rewrite the API if porting to other platform.*/ rtlglue_drvMutexLock(); _smi_start(); /* Start SMI */ _smi_writeBit(0x0b, 4); /* CTRL code: 4'b1011 for RTL8370 */ _smi_writeBit(0x4, 3); /* CTRL code: 3'b100 */ _smi_writeBit(0x1, 1); /* 1: issue READ command */ con = 0; do { con++; _smi_readBit(1, &ACK); /* ACK for issuing READ command*/ } while ((ACK != 0) && (con < ack_timer)); if (ACK != 0) ret = RT_ERR_FAILED; _smi_writeBit((mAddrs&0xff), 8); /* Set reg_addr[7:0] */ con = 0; do { con++; _smi_readBit(1, &ACK); /* ACK for setting reg_addr[7:0] */ } while ((ACK != 0) && (con < ack_timer)); if (ACK != 0) ret = RT_ERR_FAILED; _smi_writeBit((mAddrs>>8), 8); /* Set reg_addr[15:8] */ con = 0; do { con++; _smi_readBit(1, &ACK); /* ACK by RTL8369 */ } while ((ACK != 0) && (con < ack_timer)); if (ACK != 0) ret = RT_ERR_FAILED; _smi_readBit(8, &rawData); /* Read DATA [7:0] */ *rData = rawData&0xff; _smi_writeBit(0x00, 1); /* ACK by CPU */ _smi_readBit(8, &rawData); /* Read DATA [15: 8] */ _smi_writeBit(0x01, 1); /* ACK by CPU */ *rData |= (rawData<<8); _smi_stop(); rtlglue_drvMutexUnlock();/*enable CPU interrupt*/ return ret; #endif /* end of #if defined(MDC_MDIO_OPERATION) */ }