int gen_io_r(int offset)
{
uint8 ret;
uint8 temp;
uint8 has_scd = MD_IsCD ? 0x00 : 0x20;
uint8 gen_ver = 0x00; /* Version 0 hardware */
switch(offset)
{
default:
ret = 0x00;
MD_DBG(MD_DBG_WARNING, "[IO] Unmapped I/O Read: %04x\n", offset);
break;
case 0x00: /* Version */
temp = 0x00;
if(is_overseas_reported)
temp |= 0x80;
if(is_pal_reported)
temp |= 0x40;
ret = (temp | has_scd | gen_ver);
break;
case 0x01: /* Port A Data */
case 0x02: /* Port B Data */
case 0x03: /* Port C Data */
{
int wp = offset - 0x01;
UpdateBusThing(md_timestamp);
ret = (PortDataBus[wp] & 0x7F) | (PortCtrl[wp] & 0x80);
}
break;
case 0x04: /* Port A Ctrl */
case 0x05: /* Port B Ctrl */
case 0x06: /* Port C Ctrl */
ret = PortCtrl[offset - 0x04];
break;
case 0x07: /* Port A TxData */
case 0x0A: /* Port B TxData */
case 0x0D: /* Port C TxData */
ret = PortTxData[(offset - 0x07) / 3];
break;
case 0x09: /* Port A S-Ctrl */
case 0x0C: /* Port B S-Ctrl */
case 0x0F: /* Port C S-Ctrl */
ret = PortSCtrl[(offset - 0x09) / 3];
break;
}
//printf("I/O Read: %04x ret=%02x, %d @ %08x\n", offset, ret, md_timestamp, C68k_Get_PC(&Main68K));
return(ret);
}
uint16 MD_Cart_Type_RMX3::Read16(uint32 A)
{
if(A < 0x400000)
{
if(A > rom_size)
{
MD_DBG(MD_DBG_WARNING, "[MAP_RMX3] Unknown read16 from 0x%08x\n", A);
return(0);
}
return(READ_WORD_MSB(rom, A));
}
if(A == 0xa13000)
return(0x0C);
if(A == 0x400004)
return(0x88);
MD_DBG(MD_DBG_WARNING, "[MAP_RMX3] Unknown read16 from 0x%08x\n", A);
return(m68k_read_bus_16(A));
}
void MD_Cart_Type_SSF2::Write8(uint32 A, uint8 V)
{
switch(A)
{
default: MD_DBG(MD_DBG_WARNING, "[MAP_SSF2] Unknown write8 to 0x%08x, =0x%02x\n", A, V);
break;
case 0xA130F1: control = V & 0x3; break;
case 0xA130F3: sf2_banks[1] = V & 0x3F; break;
case 0xA130F5: sf2_banks[2] = V & 0x3F; break;
case 0xA130F7: sf2_banks[3] = V & 0x3F; break;
case 0xA130F9: sf2_banks[4] = V & 0x3F; break;
case 0xA130FB: sf2_banks[5] = V & 0x3F; break;
case 0xA130FD: sf2_banks[6] = V & 0x3F; break;
case 0xA130FF: sf2_banks[7] = V & 0x3F; break;
}
}
void MD_Cart_Type_SSF2::Write16(uint32 A, uint16 V)
{
// Just a guess
switch(A)
{
default: MD_DBG(MD_DBG_WARNING, "[MAP_SSF2] Unknown write16 to 0x%08x, =0x%04x\n", A, V);
break;
case 0xA130F0: control = V & 0x3; break;
case 0xA130F2: sf2_banks[1] = V & 0x3F; break;
case 0xA130F4: sf2_banks[2] = V & 0x3F; break;
case 0xA130F6: sf2_banks[3] = V & 0x3F; break;
case 0xA130F8: sf2_banks[4] = V & 0x3F; break;
case 0xA130FA: sf2_banks[5] = V & 0x3F; break;
case 0xA130FC: sf2_banks[6] = V & 0x3F; break;
case 0xA130FE: sf2_banks[7] = V & 0x3F; break;
}
}
uint8 MD_Cart_Type_SRAM::Read8(uint32 A)
{
if(sram_enabled && A >= sram_start && A <= sram_end)
{
return(READ_BYTE_MSB(sram, A - sram_start));
}
if(A < 0x400000)
{
if(A >= rom_size)
{
MD_DBG(MD_DBG_WARNING, "[MAP_SRAM] Unknown read8 from 0x%08x\n", A);
return(0);
}
return(READ_BYTE_MSB(rom, A));
}
return(m68k_read_bus_8(A));
}
