void MstarSysInit(void) { uint u32Tmp; extern MS_BOOL MDrv_MIU_SetIOMapBase(void); extern MS_BOOL MDrv_SEM_Init(void); MsOS_Init(); MDrv_MMIO_Init(); MDrv_MMIO_GetBASE((MS_U32 *)&MS_RIU_MAP, (MS_U32 *)&u32Tmp, MS_MODULE_PM); MDrv_SEM_Init(); MDrv_MIU_SetIOMapBase(); MsOS_CPU_EnableInterrupt(); #if (ENABLE_MODULE_ENV_IN_SERIAL==1) puts ("SPI: "); { extern int spi_init (void); spi_init(); /* go init the SPI */ } #if (CONFIG_MSTAR_BD_MST028B_10AFX_EAGLE||CONFIG_MSTAR_BD_MST038B_10AHT_EAGLE) MDrv_SERFLASH_SetWPInfo(TRUE); #else ms_Flash_SetHWWP_CB pCB = msFlash_ActiveFlash_Set_HW_WP; MDrv_SERFLASH_SetFlashWPCallBack(pCB); #endif #else #if(ENABLE_BOOTING_FROM_EXT_EMMC_WITH_CPU==0) MDrv_SERFLASH_Init(); #endif #endif mdrv_gpio_init(); run_command("init_raw_io" , 0); run_command("config_raw_io" , 0); }
void MstarSysInit(void) { uint u32Tmp; /*set up Mstar IRQ handler*/ extern void mhal_fiq_merge(void); extern void MAsm_CPU_TimerStart(void); extern void dcache_init(void); extern void l2_cache_init(void); mhal_fiq_merge(); MsOS_Init(); #ifdef CONFIG_SYS_DCACHE dcache_init(); #endif #ifndef CONFIG_L2_OFF l2_cache_init(); #endif #if defined(CONFIG_TIMER_TEST) MDrv_Timer_ISR_Register(); #endif MsOS_CPU_EnableInterrupt(); MAsm_CPU_TimerStart(); MDrv_MMIO_Init(); MDrv_MMIO_GetBASE((MS_U32 *)&MS_RIU_MAP, (MS_U32 *)&u32Tmp, MS_MODULE_PM); #if (ENABLE_MODULE_ENV_IN_SERIAL==1) puts ("SPI: "); { extern int spi_init (void); spi_init(); /* go init the SPI */ } #if (CONFIG_MSTAR_BD_MST028B_10AFX_EAGLE||CONFIG_MSTAR_BD_MST038B_10AHT_EAGLE) MDrv_SERFLASH_SetWPInfo(TRUE); #else ms_Flash_SetHWWP_CB pCB = msFlash_ActiveFlash_Set_HW_WP; MDrv_SERFLASH_SetFlashWPCallBack(pCB); FlashSetHWWPCB = FlashSetHWWPCB; McuChipSelectCB = McuChipSelectCB; #endif #else #if(ENABLE_BOOTING_FROM_EXT_EMMC_WITH_CPU==0) MDrv_SERFLASH_Init(); #endif #endif mdrv_gpio_init(); MDrv_BDMA_Init(MIU_INTERVAL); run_command("init_raw_io" , 0); run_command("config_raw_io" , 0); }
/* * Subroutine: do_tuner * * Description: Handler for 'tuner' command.. * * Inputs: argv[1] contains the subcommand * * Return: None * */ int do_dmx_init(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { MS_PHYADDR phyFW; MS_U8* pu8FW; DMX_FLOW_INPUT inSrc; if (argc<1) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; } inSrc = (DMX_FLOW_INPUT)simple_strtoul(argv[1], NULL, 10); MDrv_MMIO_Init(); // must init MMI before init DMX pu8FW = (MS_U8*)(((int)u8TSFwBuf + 0x7F) & (~0x7F)); pu8FW = (MS_U8*)MsOS_VA2PA((MS_U32)pu8FW); pu8FW = (MS_U8*)MsOS_PA2KSEG1((MS_U32)pu8FW); memcpy(pu8FW, u8TSPFirmware, sizeof(u8TSPFirmware)); MsOS_FlushMemory(); phyFW = (MS_PHYADDR)MsOS_VA2PA((MS_U32)pu8FW); if (DMX_FILTER_STATUS_ERROR == MApi_DMX_SetFW(phyFW, sizeof(u8TSPFirmware))) { printf("DeMux>>ERROR! SetFW fail\n"); return -1; } MApi_DMX_SetHK(TRUE); if (DMX_FILTER_STATUS_ERROR == MApi_DMX_Init()) { printf("DeMux>>ERROR! TSP init fail\n"); return -1; } #if defined(CONFIG_URANUS4) || defined(CONFIG_KRONUS) || defined(CONFIG_KAISERIN) || defined(CONFIG_KENYA) // set VQ for TSP, set FW/VQ for TSP2 MS_U8* pu8VQ; MS_PHYADDR phyVQ; DMX_TSPParam param; memset(¶m,0,sizeof(param)); pu8VQ = (MS_U8*)(((int)u8TSVQBuf + 0x7) & (~0x7)); phyVQ = (MS_PHYADDR)MsOS_VA2PA((MS_U32)pu8VQ); // printf("[%s][%d] (fw, vq) = (0x%08x 0x%08x)\n", __FUNCTION__, __LINE__, // phyFW, phyVQ); param.phyFWAddr = (MS_PHYADDR)phyFW; param.u32FWSize = TSP_FW_SIZE; param.phyVQAddr = (MS_PHYADDR)phyVQ; param.u32VQSize = TSP_VQ_SIZE;//(200*16 + 200*8 + 200*8); if (DMX_FILTER_STATUS_ERROR == MApi_DMX_TSPInit(¶m)) { printf("DeMux>>ERROR! TSP set fw/vq fail\n"); return -1; } #endif if (DMX_FILTER_STATUS_OK!= MApi_DMX_FlowSet(DMX_FLOW_PLAYBACK, inSrc, TS_CLK_INV, TRUE, TS_PARALLEL_OUTPUT)) { printf("DeMux>>ERROR! switch to demod fail\n"); return -1; } return 0; }