/* ************************************************************************* *\ * FUNCTION: mdfld_dsi_tpo_ic_init * * DESCRIPTION: This function is called only by mrst_dsi_mode_set and * restore_display_registers. since this function does not * acquire the mutex, it is important that the calling function * does! \* ************************************************************************* */ static void mdfld_dsi_tpo_ic_init(struct mdfld_dsi_config *dsi_config, u32 pipe) { struct drm_device *dev = dsi_config->dev; u32 dcsChannelNumber = dsi_config->channel_num; u32 gen_data_reg = MIPI_HS_GEN_DATA_REG(pipe); u32 gen_ctrl_reg = MIPI_HS_GEN_CTRL_REG(pipe); u32 gen_ctrl_val = GEN_LONG_WRITE; DRM_INFO("Enter mrst init TPO MIPI display.\n"); gen_ctrl_val |= dcsChannelNumber << DCS_CHANNEL_NUMBER_POS; /* Flip page order */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x00008036); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x02 << WORD_COUNTS_POS)); /* 0xF0 */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x005a5af0); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); /* Write protection key */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x005a5af1); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); /* 0xFC */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x005a5afc); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); /* 0xB7 */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x770000b7); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x00000044); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x05 << WORD_COUNTS_POS)); /* 0xB6 */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x000a0ab6); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); /* 0xF2 */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x081010f2); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x4a070708); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x000000c5); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x09 << WORD_COUNTS_POS)); /* 0xF8 */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x024003f8); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x01030a04); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x0e020220); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x00000004); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x0d << WORD_COUNTS_POS)); /* 0xE2 */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x398fc3e2); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x0000916f); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x06 << WORD_COUNTS_POS)); /* 0xB0 */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x000000b0); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x02 << WORD_COUNTS_POS)); /* 0xF4 */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x240242f4); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x78ee2002); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x2a071050); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x507fee10); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x10300710); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x14 << WORD_COUNTS_POS)); /* 0xBA */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x19fe07ba); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x101c0a31); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x00000010); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x09 << WORD_COUNTS_POS)); /* 0xBB */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x28ff07bb); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x24280a31); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x00000034); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x09 << WORD_COUNTS_POS)); /* 0xFB */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x535d05fb); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x1b1a2130); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x221e180e); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x131d2120); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x535d0508); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x1c1a2131); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x231f160d); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x111b2220); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x535c2008); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x1f1d2433); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x2c251a10); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x2c34372d); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x00000023); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x31 << WORD_COUNTS_POS)); /* 0xFA */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x525c0bfa); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x1c1c232f); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x2623190e); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x18212625); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x545d0d0e); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x1e1d2333); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x26231a10); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x1a222725); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x545d280f); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x21202635); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x31292013); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x31393d33); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x00000029); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x31 << WORD_COUNTS_POS)); /* Set DM */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x000100f7); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); }
int mdfld_dsi_pkg_sender_init(struct mdfld_dsi_connector *dsi_connector, int pipe) { struct mdfld_dsi_pkg_sender *pkg_sender; struct mdfld_dsi_config *dsi_config = mdfld_dsi_get_config(dsi_connector); struct drm_device *dev = dsi_config->dev; struct drm_psb_private *dev_priv = dev->dev_private; const struct psb_offset *map = &dev_priv->regmap[pipe]; u32 mipi_val = 0; if (!dsi_connector) { DRM_ERROR("Invalid parameter\n"); return -EINVAL; } pkg_sender = dsi_connector->pkg_sender; if (!pkg_sender || IS_ERR(pkg_sender)) { pkg_sender = kzalloc(sizeof(struct mdfld_dsi_pkg_sender), GFP_KERNEL); if (!pkg_sender) { DRM_ERROR("Create DSI pkg sender failed\n"); return -ENOMEM; } dsi_connector->pkg_sender = (void *)pkg_sender; } pkg_sender->dev = dev; pkg_sender->dsi_connector = dsi_connector; pkg_sender->pipe = pipe; pkg_sender->pkg_num = 0; pkg_sender->panel_mode = 0; pkg_sender->status = MDFLD_DSI_PKG_SENDER_FREE; /*init regs*/ /* FIXME: should just copy the regmap ptr ? */ pkg_sender->dpll_reg = map->dpll; pkg_sender->dspcntr_reg = map->cntr; pkg_sender->pipeconf_reg = map->conf; pkg_sender->dsplinoff_reg = map->linoff; pkg_sender->dspsurf_reg = map->surf; pkg_sender->pipestat_reg = map->status; pkg_sender->mipi_intr_stat_reg = MIPI_INTR_STAT_REG(pipe); pkg_sender->mipi_lp_gen_data_reg = MIPI_LP_GEN_DATA_REG(pipe); pkg_sender->mipi_hs_gen_data_reg = MIPI_HS_GEN_DATA_REG(pipe); pkg_sender->mipi_lp_gen_ctrl_reg = MIPI_LP_GEN_CTRL_REG(pipe); pkg_sender->mipi_hs_gen_ctrl_reg = MIPI_HS_GEN_CTRL_REG(pipe); pkg_sender->mipi_gen_fifo_stat_reg = MIPI_GEN_FIFO_STAT_REG(pipe); pkg_sender->mipi_data_addr_reg = MIPI_DATA_ADD_REG(pipe); pkg_sender->mipi_data_len_reg = MIPI_DATA_LEN_REG(pipe); pkg_sender->mipi_cmd_addr_reg = MIPI_CMD_ADD_REG(pipe); pkg_sender->mipi_cmd_len_reg = MIPI_CMD_LEN_REG(pipe); /*init lock*/ spin_lock_init(&pkg_sender->lock); if (mdfld_get_panel_type(dev, pipe) != TC35876X) { /** * For video mode, don't enable DPI timing output here, * will init the DPI timing output during mode setting. */ mipi_val = PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX; if (pipe == 0) mipi_val |= 0x2; REG_WRITE(MIPI_PORT_CONTROL(pipe), mipi_val); REG_READ(MIPI_PORT_CONTROL(pipe)); /* do dsi controller init */ mdfld_dsi_controller_init(dsi_config, pipe); } return 0; }