void usb_disconnect()
{
struct usb_event evt;
evt.event = USB_EVENT_DISCONNECT;
if (static_data->usb_event_cb) {
static_data->usb_event_cb(&evt);
}
if (dwc_otg_device->core_if->pcd_cb) {
DWC_FREE(dwc_otg_device->core_if->pcd_cb);
dwc_otg_device->core_if->pcd_cb = NULL;
}
if (dwc_otg_device->pcd) {
dwc_otg_pcd_remove(dwc_otg_device->pcd);
dwc_otg_device->pcd = NULL;
}
if (dwc_otg_device->core_if) {
dwc_otg_cil_remove(dwc_otg_device->core_if);
dwc_otg_device->core_if = NULL;
}
/* Disable clock */
MMIO_REG_VAL(AHB_CTRL_REG) &= ~CCU_USB_CLK_EN;
/* Stopping USB PLL */
MMIO_REG_VAL(USB_PLL_CFG0) &= ~USB_PLL_PDLD;
/* Disable regulator */
gpio_write(SOC_GPIO_32, VENABLE_USB_REGULATOR, 0);
}
static int comp_init(struct td_device *dev)
{
int i;
struct cmp_cb *cmp_cb_tmp = (struct cmp_cb *)dev->priv;
for (i = 0; i < CMP_COUNT; i++) {
cmp_cb_tmp[i].cb = NULL;
cmp_cb_tmp[i].cb_data = NULL;
}
dev->priv = cmp_cb_tmp;
#ifdef CONFIG_QUARK
MMIO_REG_VAL_FROM_BASE(SCSS_REGISTER_BASE,
INT_COMPARATORS_HOST_MASK) |=
INT_COMPARATORS_MASK;
#elif CONFIG_ARC
MMIO_REG_VAL_FROM_BASE(SCSS_REGISTER_BASE, INT_COMPARATORS_SS_MASK) |=
INT_COMPARATORS_MASK;
#endif
MMIO_REG_VAL(CMP_STAT_CLR) |= INT_COMPARATORS_MASK;
MMIO_REG_VAL(CMP_EN) &= ~(INT_COMPARATORS_MASK);
MMIO_REG_VAL(CMP_PWR) &= ~(INT_COMPARATORS_MASK);
/* enable interrupt trap for comparator driver */
IRQ_CONNECT(SOC_CMP_INTERRUPT, ISR_DEFAULT_PRIO, comp_isr, NULL, 0);
irq_enable(SOC_CMP_INTERRUPT);
return 0;
}
void board_early_init(void)
{
/* disable unused peripheral to reduce power consumption */
MMIO_REG_VAL(PERIPH_CLK_GATE_CTRL) &= ~QRK_CLK_GATE_INIT_VALUE;
MMIO_REG_VAL(SS_PERIPH_CLK_GATE_CTL) &= ~SS_CLK_GATE_INIT_VALUE;
MMIO_REG_VAL(AHB_CTRL_REG) &= ~MLAYER_CLK_GATE_INIT_VALUE;
battery_latch_en();
}
void set_clock_gate(struct clk_gate_info_s* clk_gate_info, uint32_t value)
{
uint32_t tmp ;
tmp = MMIO_REG_VAL(clk_gate_info->clk_gate_register);
tmp &= ~(clk_gate_info->bits_mask);
tmp |= ((clk_gate_info->bits_mask) & value);
MMIO_REG_VAL(clk_gate_info->clk_gate_register) = tmp;
}
void platform_usb_release()
{
/* Disable clock */
MMIO_REG_VAL(AHB_CTRL_REG) &= ~CCU_USB_CLK_EN;
/* Stopping USB PLL */
MMIO_REG_VAL(USB_PLL_CFG0) &= ~USB_PLL_PDLD;
/* Disable regulator */
gpio_write(SOC_GPIO_32, 28, 0);
}
DRIVER_API_RC comp_disable(int index)
{
if (index >= CMP_COUNT || index < 0) {
return DRV_RC_INVALID_CONFIG;
}
// Disable comparator <index>
MMIO_REG_VAL(CMP_EN) &= ~(1 << index);
// Disable power in comparator <index>
MMIO_REG_VAL(CMP_PWR) &= ~(1 << index);
return DRV_RC_OK;
}
void analogWrite(uint8_t pin, uint32_t val)
{
if (! digitalPinHasPWM(pin))
{
if(val > 127)
{
digitalWrite(pin, HIGH);
}
else
{
digitalWrite(pin, LOW);
}
return;
}
if (val <= 0) {
/* Use GPIO for 0% duty cycle (always off) */
pinMode(pin, OUTPUT);
digitalWrite(pin, LOW);
} else if (val >= ((1 << _writeResolution) - 1)) {
/* Use GPIO for 100% duty cycle (always on) */
pinMode(pin, OUTPUT);
digitalWrite(pin, HIGH);
} else {
/* PWM for everything in between */
PinDescription *p = &g_APinDescription[pin];
uint32_t offset;
uint32_t hcnt = (val/(float)maxResolutionValue) * pwmPeriod[p->ulPwmChan];
uint32_t lcnt = pwmPeriod[p->ulPwmChan] - hcnt;
/* Set the high count period (duty cycle) */
offset = ((p->ulPwmChan * QRK_PWM_N_LCNT2_LEN) + QRK_PWM_N_LOAD_COUNT2);
MMIO_REG_VAL(QRK_PWM_BASE_ADDR + offset) = hcnt;
/* Set the low count period (duty cycle) */
offset = ((p->ulPwmChan * QRK_PWM_N_REGS_LEN) + QRK_PWM_N_LOAD_COUNT1);
MMIO_REG_VAL(QRK_PWM_BASE_ADDR + offset) = lcnt;
/* start the PWM output */
offset = ((p->ulPwmChan * QRK_PWM_N_REGS_LEN) + QRK_PWM_N_CONTROL);
SET_MMIO_MASK(QRK_PWM_BASE_ADDR + offset, QRK_PWM_CONTROL_ENABLE);
if(pinmuxMode[pin] != PWM_MUX_MODE)
{
/* Disable pull-up and set pin mux for PWM output */
SET_PIN_PULLUP(p->ulSocPin, 0);
SET_PIN_MODE(p->ulSocPin, PWM_MUX_MODE);
pinmuxMode[pin] = PWM_MUX_MODE;
}
}
}
void platform_usb_init(void)
{
/* platform specific init of USB core */
MMIO_REG_VAL(QRK_PMUX_SLEW_RATE_0) = PIN_MUX_SLEW_4mA_driver;
MMIO_REG_VAL(QRK_PMUX_SLEW_RATE_1) = PIN_MUX_SLEW_4mA_driver;
MMIO_REG_VAL(QRK_PMUX_SLEW_RATE_2) = PIN_MUX_SLEW_4mA_driver;
MMIO_REG_VAL(QRK_PMUX_SLEW_RATE_3) = PIN_MUX_SLEW_4mA_driver;
enable_usb();
/* Init the USB driver */
SCSS_REG_VAL(SCSS_INT_USB_MASK_OFFSET) = QRK_INT_USB_UNMASK_QRK;
}
static int comp_resume(struct td_device *dev)
{
irq_enable(SOC_CMP_INTERRUPT);
// Clear interrupt flag to enable interrupts after resume
MMIO_REG_VAL(CMP_STAT_CLR) = ~0;
return 0;
}
void usb_connect()
{
gpio_cfg_data_t config;
/* Setup and turn on USB PLL */
MMIO_REG_VAL(USB_PLL_CFG0) = USB_PLL_CFG0_DEFAULT | USB_PLL_PDLD;
/*Wait for the PLL lock */
int count = 500;
while(count-- && (0 == (MMIO_REG_VAL(USB_PLL_CFG0) & USB_PLL_LOCK))){}
/* Turn on the clock gate */
MMIO_REG_VAL(AHB_CTRL_REG) |= CCU_USB_CLK_EN;
/* GPIO already configured by BOOTLOADER on OUTPUT MODE */
/* Enable internal regulator */
soc_gpio_write(SOC_GPIO_32, VENABLE_USB_REGULATOR, 1);
}
void variantPwmInit(void)
{
/* Enable PWM peripheral clock */
MMIO_REG_VAL(QRK_CLKGATE_CTRL) |= QRK_CLKGATE_CTRL_PWM_ENABLE;
/* Select PWM mode, with interrupts masked */
for (uint8_t i = 0; i < NUM_PWM; i++) {
uint32_t offset = ((i * QRK_PWM_N_REGS_LEN) + QRK_PWM_N_CONTROL);
MMIO_REG_VAL_FROM_BASE(QRK_PWM_BASE_ADDR, offset) = QRK_PWM_CONTROL_PWM_OUT | QRK_PWM_CONTROL_INT_MASK | QRK_PWM_CONTROL_MODE_PERIODIC;
}
}
void SPIClass::begin()
{
/* Protect from a scheduler and prevent transactionBegin*/
uint32_t flags = interrupt_lock();
if (!initialized) {
interruptMode = 0;
interruptMask[0] = 0;
interruptMask[1] = 0;
interruptMask[2] = 0;
#ifdef SPI_TRANSACTION_MISMATCH_LED
inTransactionFlag = 0;
#endif
lsbFirst = false;
frameSize = SPI_8_BIT;
/* Set SS to high so a connected chip will be "deselected" by default.
* TODO - confirm that data register is updated even if pin is set as
* input. */
digitalWrite(ss_gpio, HIGH);
/* When the SS pin is set as OUTPUT, it can be used as
* a general purpose output port (it doesn't influence
* SPI operations). */
pinMode(ss_gpio, OUTPUT);
/* disable controller */
SPI_M_REG_VAL(spi_addr, SPIEN) &= SPI_DISABLE;
/* Enable clock to peripheral */
MMIO_REG_VAL(PERIPH_CLK_GATE_CTRL) |= enable_val;
/* Configure defaults for clock divider, frame size and data mode */
SPI_M_REG_VAL(spi_addr, BAUDR) = SPI_CLOCK_DIV4;
SPI_M_REG_VAL(spi_addr, CTRL0) =
(frameSize << SPI_FSIZE_SHIFT) | (SPI_MODE0 << SPI_MODE_SHIFT);
/* Disable interrupts */
SPI_M_REG_VAL(spi_addr, IMR) = SPI_DISABLE_INT;
/* Enable at least one slave device (mandatory, though
* SS signals are unused) */
SPI_M_REG_VAL(spi_addr, SER) = 0x1;
/* Enable controller */
SPI_M_REG_VAL(spi_addr, SPIEN) |= SPI_ENABLE;
/* Set SoC pin mux configuration */
SET_PIN_MODE(g_APinDescription[MOSI].ulSocPin, SPI_MUX_MODE);
SET_PIN_MODE(g_APinDescription[MISO].ulSocPin, SPI_MUX_MODE);
SET_PIN_MODE(g_APinDescription[SCK].ulSocPin, SPI_MUX_MODE);
}
initialized++; /* reference count */
interrupt_unlock(flags);
}
void comp_isr()
{
struct cmp_cb *cmp_cb_tmp ;
struct device* comparator_dev = &pf_device_soc_comparator;
int i;
cmp_cb_tmp = (struct cmp_cb*)(comparator_dev->priv);
for (i = 0; i < CMP_COUNT; i++) {
if (MMIO_REG_VAL(CMP_STAT_CLR) & (1 << i)) {
comp_disable(i);
if (cmp_cb_tmp[i].cb != NULL) {
cmp_cb_tmp[i].cb(cmp_cb_tmp[i].cb_data);
} else {
pr_debug(LOG_MODULE_DRV,
"Unexpected comparator interrupt: %d",
i);
}
// Clear interrupt status to process next IRQ
MMIO_REG_VAL(CMP_STAT_CLR) |= (1 << i);
}
}
}
/**
* Enables USB driver clock and regulator.
*/
static void enable_usb()
{
gpio_cfg_data_t config;
/* Setup and turn on USB PLL */
MMIO_REG_VAL(USB_PLL_CFG0) = USB_PLL_CFG0_DEFAULT | USB_PLL_PDLD;
/*Wait for the PLL lock */
int count = 500;
while (count-- && (0 == (MMIO_REG_VAL(USB_PLL_CFG0) & USB_PLL_LOCK))) {
}
/* Turn on the clock gate */
MMIO_REG_VAL(AHB_CTRL_REG) |= CCU_USB_CLK_EN;
pr_info("USB PLL Configured count: %d\n", count);
/* activate regulator after USB clocks are stabilized */
config.gpio_type = GPIO_OUTPUT;
gpio_set_config(SOC_GPIO_32, VENABLE_USB_REGULATOR, &config);
gpio_write(SOC_GPIO_32, VENABLE_USB_REGULATOR, 1);
}
void SPIClass::end() {
uint32_t flags = interrupt_lock(); // Protect from a scheduler and prevent transactionBegin
// Decrease the reference counter
if (initialized)
initialized--;
// If there are no more references disable SPI
if (!initialized) {
SPI1_M_REG_VAL(SPIEN) &= SPI_DISABLE;
MMIO_REG_VAL(PERIPH_CLK_GATE_CTRL) &= DISABLE_SPI_MASTER_1;
#ifdef SPI_TRANSACTION_MISMATCH_LED
inTransactionFlag = 0;
#endif
}
interrupt_unlock(flags);
}
void SPIClass::end() {
/* Protect from a scheduler and prevent transactionBegin */
uint32_t flags = interrupt_lock();
/* Decrease the reference counter */
if (initialized)
initialized--;
/* If there are no more references disable SPI */
if (!initialized) {
SPI_M_REG_VAL(spi_addr, SPIEN) &= SPI_DISABLE;
MMIO_REG_VAL(PERIPH_CLK_GATE_CTRL) &= disable_val;
#ifdef SPI_TRANSACTION_MISMATCH_LED
inTransactionFlag = 0;
#endif
}
interrupt_unlock(flags);
}
void dfu_spi_init(void){
/* pinmuxing */
SET_PIN_MODE(55, QRK_PMUX_SEL_MODEB); /* SPI0_M_SCK */
SET_PIN_MODE(56, QRK_PMUX_SEL_MODEB); /* SPI0_M_MISO */
SET_PIN_MODE(57, QRK_PMUX_SEL_MODEB); /* SPI0_M_MOSI */
/* SPI0_M CS is controlled as a gpio */
SET_PIN_MODE(58, QRK_PMUX_SEL_MODEA); /* GPIO[24]/SPI0_M_CS_0 */
/* spi0 clock gating */
MMIO_REG_VAL(PERIPH_CLK_GATE_CTRL) |= SPI0_CLK_GATE_MASK;
spi_cfg_data_t spi_cfg;
spi_cfg.speed = 4000; /*!< SPI bus speed in KHz */
spi_cfg.txfr_mode = SPI_TX_RX; /*!< Transfer mode */
spi_cfg.data_frame_size = SPI_8_BIT; /*!< Data Frame Size ( 4 - 16 bits ) */
spi_cfg.bus_mode = SPI_BUSMODE_0; /*!< SPI bus mode is 0 by default */
soc_spi_set_config(&spi_cfg);
}
int digitalRead( uint8_t pin )
{
if (pin >= NUM_DIGITAL_PINS) return LOW;
PinDescription *p = &g_APinDescription[pin];
if (p->ulGPIOType == SS_GPIO)
{
uint32_t reg = p->ulGPIOBase + SS_GPIO_EXT_PORTA;
if (READ_ARC_REG(reg) & (1 << p->ulGPIOId)) return HIGH;
}
else if (p->ulGPIOType == SOC_GPIO)
{
uint32_t reg = p->ulGPIOBase + SOC_GPIO_EXT_PORTA;
if (MMIO_REG_VAL(reg) & (1 << p->ulGPIOId)) return HIGH;
}
return LOW;
}
DRIVER_API_RC comp_configure(struct td_device *dev, int index, int polarity,
int refsel, void (*cb)(void *), void *param)
{
struct cmp_cb *cmp_cb_tmp = (struct cmp_cb *)dev->priv;
if (index >= CMP_COUNT || index < 0) {
return DRV_RC_INVALID_CONFIG;
}
cmp_cb_tmp[index].cb = cb;
cmp_cb_tmp[index].cb_data = param;
// Enable comparator <index>
MMIO_REG_VAL(CMP_PWR) |= (1 << index);
if (polarity)
MMIO_REG_VAL(CMP_REF_POL) |= (1 << index);
else
MMIO_REG_VAL(CMP_REF_POL) &= ~(1 << index);
if (refsel)
MMIO_REG_VAL(CMP_REF_SEL) |= (1 << index);
else
MMIO_REG_VAL(CMP_REF_SEL) &= ~(1 << index);
// Enable power in comparator <index>
MMIO_REG_VAL(CMP_EN) |= (1 << index);
/* Enable interrupt to host. */
#ifdef CONFIG_QUARK
MMIO_REG_VAL_FROM_BASE(SCSS_REGISTER_BASE,
INT_COMPARATORS_HOST_MASK) &=
~(1 << index);
#elif CONFIG_ARC
MMIO_REG_VAL_FROM_BASE(SCSS_REGISTER_BASE, INT_COMPARATORS_SS_MASK) &=
~(1 << index);
#else
#error Unknown target for comparator driver
#endif
return DRV_RC_OK;
}
static int comp_resume(struct device* dev)
{
// Clear interrupt flag to enable interrupts after resume
MMIO_REG_VAL(CMP_STAT_CLR) = ~0;
return 0;
}
