示例#1
0
/*
** Function to setup MMU. This function Maps three regions (1. DDR
** 2. OCMC and 3. Device memory) and enables MMU.
*/
void MMUConfigAndEnable(void)
{
    /*
    ** Define DDR memory region of AM335x. DDR can be configured as Normal
    ** memory with R/W access in user/privileged modes. The cache attributes
    ** specified here are,
    ** Inner - Write through, No Write Allocate
    ** Outer - Write Back, Write Allocate
    */
    REGION regionDdr = {
                        MMU_PGTYPE_SECTION, START_ADDR_DDR, NUM_SECTIONS_DDR,
                        MMU_MEMTYPE_NORMAL_NON_SHAREABLE(MMU_CACHE_WT_NOWA,
                                                     MMU_CACHE_WB_WA),
                        MMU_REGION_NON_SECURE, MMU_AP_PRV_RW_USR_RW,
                        (unsigned int*)pageTable
                       };
    /*
    ** Define OCMC RAM region of AM335x. Same Attributes of DDR region given.
    */
    REGION regionOcmc = {
                         MMU_PGTYPE_SECTION, START_ADDR_OCMC, NUM_SECTIONS_OCMC,
                         MMU_MEMTYPE_NORMAL_NON_SHAREABLE(MMU_CACHE_WT_NOWA,
                                                      MMU_CACHE_WB_WA),
                         MMU_REGION_NON_SECURE, MMU_AP_PRV_RW_USR_RW,
                         (unsigned int*)pageTable
                        };

    /*
    ** Define Device Memory Region. The region between OCMC and DDR is
    ** configured as device memory, with R/W access in user/privileged modes.
    ** Also, the region is marked 'Execute Never'.
    */
    REGION regionDev = {
                        MMU_PGTYPE_SECTION, START_ADDR_DEV, NUM_SECTIONS_DEV,
                        MMU_MEMTYPE_DEVICE_SHAREABLE,
                        MMU_REGION_NON_SECURE,
                        MMU_AP_PRV_RW_USR_RW  | MMU_SECTION_EXEC_NEVER,
                        (unsigned int*)pageTable
                       };

    /* Initialize the page table and MMU */
    MMUInit((unsigned int*)pageTable);

    /* Map the defined regions */
    MMUMemRegionMap(&regionDdr);
    MMUMemRegionMap(&regionOcmc);
    MMUMemRegionMap(&regionDev);

    /* Now Safe to enable MMU */
    MMUEnable((unsigned int*)pageTable);
}
示例#2
0
void MMUConfigAndEnablePages(void)
{
	int32_t status;
	uint32_t *lastAddr;

		mmuMemRegionConfig_t regionDdr =
					{
						START_ADDR_DDR,
						(128*1024/4), /* Number of pages */
						4096, /* Page size */
						MMU_MEM_ATTR_NORMAL_NON_SHAREABLE,
						MMU_CACHE_POLICY_WB_WA, /* Inner */
						MMU_CACHE_POLICY_WB_WA, /* Outer */
						MMU_ACCESS_CTRL_PRV_RW_USR_RW,
						FALSE /* Non Secure memory */
					};

		/** \brief Define OCMC RAM region. */
		/* TODO: Get OCMC RAM base address and size from chipdb. */
		mmuMemRegionConfig_t regionOcmc =
					{
						START_ADDR_OCMC,
						(1*1024/4), /* Number of pages */
						4096, /* Page size */
						MMU_MEM_ATTR_NORMAL_NON_SHAREABLE,
						MMU_CACHE_POLICY_WT_NOWA, /* Inner */
						MMU_CACHE_POLICY_WB_WA, /* Outer */
						MMU_ACCESS_CTRL_PRV_RW_USR_RW,
						FALSE /* Non Secure memory */
					};

		/** \brief Define Device Memory Region. The region between OCMC and DDR is
		 *         configured as device memory, with R/W access in user/privileged
		 *         modes. Also, the region is marked 'Execute Never'.
		 */
		mmuMemRegionConfig_t regionDev =
					{
						START_ADDR_DEV,
						(960*1024/4), /* Number of pages */
						4096, /* Page size */
						MMU_MEM_ATTR_DEVICE_SHAREABLE,
						MMU_CACHE_POLICY_WB_WA, /* Inner - Invalid here */
						MMU_CACHE_POLICY_WB_WA, /* Outer - Invalid here */
						MMU_ACCESS_CTRL_PRV_RW_USR_RW,
						FALSE /* Non Secure memory */
					};
		   /* Initialize the MMU */
			MMUInitEx();

		    /* Map the defined regions */
			status = MMUMemRegionMapEx(&regionDdr, (uint32_t*)pageTable1, (uint32_t*)pageTable2, TRUE, &lastAddr);
			if(status != S_PASS)
			{
				exit(-1);
			}
		    status = MMUMemRegionMapEx(&regionOcmc, (uint32_t*)pageTable1, (uint32_t*)pageTable2, TRUE, &lastAddr);
			if(status != S_PASS)
			{
				exit(-1);
			}
		    status = MMUMemRegionMapEx(&regionDev, (uint32_t*)pageTable1, (uint32_t*)pageTable2, TRUE, &lastAddr);
			if(status != S_PASS)
			{
				exit(-1);
			}

		    /* Now Safe to enable MMU */
		    MMUEnable((unsigned int*)pageTable1);
}