示例#1
0
文件: mmu.c 项目: EasternRise/AGV
void MMU_Init(void)
{
    int i,j;
    //========================== IMPORTANT NOTE =========================
    //The current stack and code area can't be re-mapped in this routine.
    //If you want memory map mapped freely, your own sophiscated MMU
    //initialization code is needed.
    //===================================================================

    MMU_DisableDCache();
    MMU_DisableICache();

    //If write-back is used,the DCache should be cleared.
    for(i=0;i<64;i++)
    	for(j=0;j<8;j++)
    	    MMU_CleanInvalidateDCacheIndex((i<<26)|(j<<5));
    MMU_InvalidateICache();
    
    #if 0
    //To complete MMU_Init() fast, Icache may be turned on here.
    MMU_EnableICache(); 
    #endif
    
    MMU_DisableMMU();
    MMU_InvalidateTLB();

    //MMU_SetMTT(int vaddrStart,int vaddrEnd,int paddrStart,int attr)
    //MMU_SetMTT(0x00000000,0x07f00000,0x00000000,RW_CNB);  //bank0
    MMU_SetMTT(0x00000000,0x03f00000,(int)__ENTRY,RW_CB);  //bank0
    MMU_SetMTT(0x04000000,0x07f00000,0,RW_NCNB);  			//bank0
    MMU_SetMTT(0x08000000,0x0ff00000,0x08000000,RW_CNB);  //bank1
    MMU_SetMTT(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2
    MMU_SetMTT(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3
    //MMU_SetMTT(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4
    MMU_SetMTT(0x20000000,0x27f00000,0x20000000,RW_CNB); //bank4 for STRATA Flash
    MMU_SetMTT(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5
    //30f00000->30100000, 31000000->30200000
    MMU_SetMTT(0x30000000,0x30100000,0x30000000,RW_CB);	  //bank6-1
    MMU_SetMTT(0x30200000,0x33e00000,0x30200000,RW_NCNB); //bank6-2
    //
    MMU_SetMTT(0x33f00000,0x33f00000,0x33f00000,RW_CB);   //bank6-3
    MMU_SetMTT(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7
    
    MMU_SetMTT(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR
    MMU_SetMTT(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR
    MMU_SetMTT(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR
    MMU_SetMTT(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used

    
    MMU_SetTTBase(_MMUTT_STARTADDRESS);//设置一级映射描述符表的基地址
    MMU_SetDomain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR);//ARM处理器的16个域的访问权限
    	//DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked)
    MMU_SetProcessId(0x0);//设置进程标识符
    MMU_EnableAlignFault();//使能地址对齐检查功能
    	
    MMU_EnableMMU();
    MMU_EnableICache();
    MMU_EnableDCache(); //DCache should be turned on after MMU is turned on.
}    
示例#2
0
static void hal_mmu_init(void)
{
    acoral_32 i,j;
    /*========================== IMPORTANT NOTE =========================*/
    /*The current stack and code area can't be re-mapped in this routine.*/
    /*If you want memory map mapped freely, your own sophiscated MMU*/
    /*initialization code is needed.*/
    /*===================================================================*/

    MMU_DisableDCache();
    MMU_DisableICache();

    /*If write-back is used,the DCache should be cleared.*/
    for(i=0;i<64;i++)
    	for(j=0;j<8;j++)
    	    MMU_CleanInvalidateDCacheIndex((i<<26)|(j<<5));
    MMU_InvalidateICache();

    #if 0
    /*To complete MMU_Init() fast, Icache may be turned on here.*/
    MMU_EnableICache();
    #endif

    MMU_DisableMMU();
    MMU_InvalidateTLB();
    /*hal_mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr)*/
    /*hal_mmu_setmtt(0x00000000,0x07f00000,0x00000000,RW_CNB);  /*bank0*/
    hal_mmu_setmtt(0x00000000,0x03f00000,__ENTRY,RW_CB);  /*bank0*/
    hal_mmu_setmtt(0x04000000,0x07f00000,0,RW_NCNB);  			/*bank0*/
    hal_mmu_setmtt(0x08000000,0x0ff00000,0x08000000,RW_CNB);  /*bank1*/
    hal_mmu_setmtt(0x10000000,0x17f00000,0x10000000,RW_NCNB); /*bank2*/
    hal_mmu_setmtt(0x18000000,0x1ff00000,0x18000000,RW_NCNB); /*bank3*/
    /*hal_mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CB); /*bank4*/
    hal_mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CNB); /*bank4 for STRATA Flash*/
    hal_mmu_setmtt(0x28000000,0x2ff00000,0x28000000,RW_NCNB); /*bank5*/
    /*30f00000->30100000, 31000000->30200000*/
    hal_mmu_setmtt(0x30000000,0x30100000,0x30000000,RW_NCNB);	  /*bank6-1*/
    hal_mmu_setmtt(0x30200000,0x33e00000,0x30200000,RW_NCNB); /*bank6-2*/
    /**/
    hal_mmu_setmtt(0x33f00000,0x33f00000,0x33f00000,RW_NCNB);   /*bank6-3*/
    hal_mmu_setmtt(0x38000000,0x3ff00000,0x38000000,RW_NCNB); /*bank7*/

    hal_mmu_setmtt(0x40000000,0x47f00000,0x40000000,RW_NCNB); /*SFR*/
    hal_mmu_setmtt(0x48000000,0x5af00000,0x48000000,RW_NCNB); /*SFR*/
    hal_mmu_setmtt(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); /*SFR*/
    hal_mmu_setmtt(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);/*not used*/


    MMU_SetTTBase(&MMU_base);
    MMU_SetDomain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR);
    	/*DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked)*/
    MMU_SetProcessId(0x0);
    MMU_EnableAlignFault();
    MMU_EnableMMU();
    MMU_EnableICache();
    MMU_EnableDCache(); /*DCache should be turned on after MMU is turned on.*/
}
示例#3
0
void MMU_Init(void)
{
	int i,j;
	MMU_DisableDCache();
	MMU_DisableICache();
	for(i=0;i<64;i++)
		for(j=0;j<8;j++)
		MMU_CleanInvalidateDCacheIndex((i<<26)|(j<<5));
		MMU_InvalidateICache();
		#if 0
		MMU_EnableICache();
		#endif
		MMU_DisableMMU();
		MMU_InvalidateTLB();
	MMU_SetMTT(0x00000000,0x03f00000,(int)__ENTRY,RW_CB);  //bank0
    MMU_SetMTT(0x04000000,0x07f00000,0,RW_NCNB);  			//bank0
    MMU_SetMTT(0x08000000,0x0ff00000,0x08000000,RW_CNB);  //bank1
    MMU_SetMTT(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2
    MMU_SetMTT(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3
    //MMU_SetMTT(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4
    MMU_SetMTT(0x20000000,0x27f00000,0x20000000,RW_CNB); //bank4 for STRATA Flash
    MMU_SetMTT(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5
    //30f00000->30100000, 31000000->30200000
    MMU_SetMTT(0x30000000,0x30100000,0x30000000,RW_CB);	  //bank6-1
    MMU_SetMTT(0x30200000,0x33e00000,0x30200000,RW_NCNB); //bank6-2
    //
    MMU_SetMTT(0x33f00000,0x33f00000,0x33f00000,RW_CB);   //bank6-3
    MMU_SetMTT(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7
    
    MMU_SetMTT(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR
    MMU_SetMTT(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR
    MMU_SetMTT(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR
    MMU_SetMTT(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used

    
    MMU_SetTTBase(_MMUTT_STARTADDRESS);
    MMU_SetDomain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR); 
    	//DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked)
    MMU_SetProcessId(0x0);
    MMU_EnableAlignFault();
    	
    MMU_EnableMMU();
    MMU_EnableICache();
    MMU_EnableDCache(); //
}
示例#4
0
文件: mmu.c 项目: EasternRise/AGV
// attr=RW_CB,RW_CNB,RW_NCNB,RW_FAULT
void ChangeRomCacheStatus(int attr)
{
    int i,j;
    MMU_DisableDCache();
    MMU_DisableICache();
    //If write-back is used,the DCache should be cleared.
    for(i=0;i<64;i++)
    	for(j=0;j<8;j++)
    	    MMU_CleanInvalidateDCacheIndex((i<<26)|(j<<5));
    MMU_InvalidateICache();
    MMU_DisableMMU();
    MMU_InvalidateTLB();
    MMU_SetMTT(0x00000000,0x07f00000,0x00000000,attr);	//bank0
    MMU_SetMTT(0x08000000,0x0ff00000,0x08000000,attr);	//bank1
    MMU_EnableMMU();
    MMU_EnableICache();
    MMU_EnableDCache();
}    
示例#5
0
void MMU_Init(void)
{
    int i,j;
    unsigned long * pTT;
    //========================== IMPORTANT NOTE =========================
    //The current stack and code area can't be re-mapped in this routine.
    //If you want memory map mapped freely, your own sophiscated MMU
    //initialization code is needed.
    //===================================================================

	Uart_Printf("MMU_Init test 1\n");
    MMU_DisableDCache();
    MMU_DisableICache();

	Uart_Printf("MMU_Init test 2\n");
    //If write-back is used,the DCache should be cleared.
    for(i=0;i<64;i++)
    	for(j=0;j<8;j++)
    	    MMU_CleanInvalidateDCacheIndex((i<<26)|(j<<5));
    MMU_InvalidateICache();
    
    #if 0
    //To complete MMU_Init() fast, Icache may be turned on here.
    MMU_EnableICache(); 
    #endif
    
    Uart_Printf("MMU_Init test 3\n");
    MMU_DisableMMU();
    Uart_Printf("MMU_Init test 4\n");
    MMU_InvalidateTLB();
 
 	Uart_Printf("MMU_Init test 5\n");
    MMU_SetMTT(0x00000000,0xffffffff,0,RW_FAULT);  //bank0
    	
           
    MMU_SetMTT(0x00000000,0x08000000,(int)__ENTRY,RW_NCNB);  //bank0
    MMU_SetMTT(0x50000000,0x58000000,0x50000000,RW_NCNB);  //bank0
    
    
    MMU_SetMTT(0x70000000,0x70400000,0x70000000,RW_NCNB);  //bank0
    MMU_SetMTT(0x71000000,0x71400000,0x71000000,RW_NCNB);  //bank0
    
    MMU_SetMTT(0x72000000,0x73200000,0x72000000,RW_NCNB);  //bank0
    MMU_SetMTT(0x74000000,0x74500000,0x74000000,RW_NCNB);  //bank0
    MMU_SetMTT(0x75000000,0x75400000,0x75000000,RW_NCNB);  //bank0
    MMU_SetMTT(0x76000000,0x76400000,0x76000000,RW_NCNB);  //bank0
    MMU_SetMTT(0x77000000,0x77300000,0x77000000,RW_NCNB);  //bank0
    MMU_SetMTT(0x78000000,0x78c00000,0x78000000,RW_NCNB);  //bank0
    MMU_SetMTT(0x7c000000,0x7c500000,0x7c000000,RW_NCNB);  //bank0
    MMU_SetMTT(0x7d000000,0x7e100000,0x7d000000,RW_NCNB);  //bank0
    
    MMU_SetMTT(0x7f000000,0x7f100000,0x7f000000,RW_NCNB);  //bank0
    

    MMU_SetMTT(0xc0000000,0xc8000000,0x50000000,RW_NCNB);
    
    
    
    //[email protected] test
    //MMU_SetMTT(0x60000000,0x68000000,0x50000000,RW_NCNB);  //bank0
    
    
    
    MMU_SetTTBase(_MMUTT_STARTADDRESS);
    MMU_SetDomain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR); 
    	//DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked)
   	MMU_SetProcessId(0x0);
    MMU_EnableAlignFault();
    	
    MMU_EnableMMU();
    
    
    
    MMU_EnableICache();
    MMU_EnableDCache(); //DCache should be turned on after MMU is turned on.
}    
示例#6
0
void Test_CpuSpeed(void)
{
    int i,j,base;
    U32 uLockPt,bypass;

	// added for testing 2410.
    Uart_Printf("[CPU Core Speed Test]\n");

	// Set MMU enable and on/off I/D-cache.
	Uart_Printf("[MMU enable]\n");
	MMU_EnableMMU();
    Uart_Printf("[ICache enable]\n");
	MMU_EnableICache();
    Uart_Printf("[DCache enable]\n");
	MMU_EnableDCache(); //DCache should be turned on after MMU is turned on.

    Uart_Printf("[FCLK:HCLK:PCLK] = [%d:%d:%d]MHz\n", FCLK/1000000, HCLK/1000000, PCLK/1000000);
    Uart_Printf("DCache locked area: %xH~%xH\n", TEST_STADDR, TEST_ENDADDR);
    Uart_Printf("ICache locked area: %x~%x(256B boundary)\n",
    	(U32)CpuSpeedFunc1,(U32)CpuSpeedFunc2);
    Uart_Printf("LCD is disabled.\n");
    //LCD_DisplayControl(0);
    rLCDCON1&=~1; // ENVID=OFF
    LED_DISPLAY(0x1);	// LED 1

    //Uart_Printf("Press any key.\n");
    //Uart_Getch();

 	Uart_Printf("Cache lock-down.\n");
	
	
    //========== ICache lock-down ==========
    MMU_SetICacheLockdownBase(10<<26);  	// The following code will be filled between cache line 10~63.
    base=10;
    bypass=1;
    uLockPt=(U32)CpuSpeedFunc1&0xffffffe0;

    for(;uLockPt<(U32)CpuSpeedFunc2;uLockPt+=0x20)
    {
        if(((uLockPt%0x100)==0)&&(uLockPt>(U32)CpuSpeedFunc1)) base++;
        #if WHICH_CPU==5410
			MMU_InvalidateICacheVA(uLockPt);
		#else	// 2410
			MMU_InvalidateICacheMVA(uLockPt);
		#endif
        if(bypass==1) MMU_SetICacheLockdownBase(base<<26);  
		#if WHICH_CPU==5410
	    	MMU_PrefetchICacheVA(uLockPt);
		#else	//2410
			MMU_PrefetchICacheMVA(uLockPt);
		#endif
    	if(bypass==1) //to put the current code outside base 9
    	{
    	    bypass=0;
    	    base=0;
            uLockPt-=0x20; //restore uLockPt
    	}
    }
    base++;
    MMU_SetICacheLockdownBase(base<<26);  // 256

    if(base>10)
    	Uart_Printf("ERROR:ICache lockdown base overflow\n");
    
    Uart_Printf("lockdown ICache line=0~%d\n",base-1);


    //========== DCache lock-down ==========
    base=0;
    uLockPt=(U32)CpuSpeedFunc1&0xffffffe0;

    //Function should be cached in DCache because of the literal pool(LDR Rn,=0xxxxx). ??
    for(;uLockPt<(U32)CpuSpeedFunc2;uLockPt+=0x20)
    {
    	if(((uLockPt%0x100)==0)&&(uLockPt>(U32)CpuSpeedFunc1))
    	    base++;
		#if WHICH_CPU==5410
    	MMU_CleanInvalidateDCacheVA(uLockPt);
		#else	//2410
    	MMU_CleanInvalidateDCacheMVA(uLockPt);
		#endif

        MMU_SetDCacheLockdownBase(base<<26);  
	    *((volatile U32 *)(uLockPt));
    }
    base++;
    MMU_SetDCacheLockdownBase(base<<26);  


    for(i=TEST_STADDR;i<TEST_ENDADDR;i+=4)*((U32 *)i)=0x55555555;
    
    for(i=0;i<0x100;i+=0x20)
    {
		#if WHICH_CPU==5410
      	MMU_CleanInvalidateDCacheVA(TEST_STADDR+i);
		#else	//2410
      	MMU_CleanInvalidateDCacheMVA(TEST_STADDR+i);
		#endif

        MMU_SetDCacheLockdownBase(base<<26);  
        *((volatile U32 *)(TEST_STADDR+i));
    }

    base++;
    MMU_SetDCacheLockdownBase(base<<26);  


   	
    Uart_Printf("lockdown DCache line=0~%d\n",base-1);


    //========== Check the line is really cache-filled ==========
#if 1
    for(uLockPt=(U32)CpuSpeedFunc1;uLockPt<(U32)CpuSpeedFunc2-4*8;uLockPt+=4)
    {
	//*((U32 *)uLockPt)=0xffffffff; //*((U32 *)uLockPt);
	*((U32 *)uLockPt)=*((U32 *)uLockPt);
    }
#endif    	
// SDRAM Self refresh
	
	LED_DISPLAY(0x2);

	//rPWRSAV |= 1<<2;	// SDRAM1 self refresh.
    CpuSpeedFunc1();

}    
示例#7
0
void MMU_Init(void)
{
    int i,j;
    //========================== IMPORTANT NOTE =========================
    //The current stack and code area can't be re-mapped in this routine.
    //If you want memory map mapped freely, your own sophiscated MMU
    //initialization code is needed.
    //===================================================================

    MMU_DisableDCache();
    MMU_DisableICache();

    //If write-back is used,the DCache should be cleared.
    for(i=0;i<64;i++)
        for(j=0;j<8;j++)
            MMU_CleanInvalidateDCacheIndex((i<<26)|(j<<5));
    MMU_InvalidateICache();

    #if 0
    //To complete MMU_Init() fast, Icache may be turned on here.
    MMU_EnableICache();
    #endif

    MMU_DisableMMU();
    MMU_InvalidateTLB();

    //MMU_SetMTT(int wVSAddr,int wVEAddr,int wPSAddr,int wAttrib)

#ifdef MY_SPL_BOARD

    MMU_SetMTT(0x00000000,0x07f00000,0x00000000,RW_CNB);  //bank0
    MMU_SetMTT(0x08000000,0x081FFFFF,0x08000000,RW_CNB);  //bank1
    MMU_SetMTT(0x10000000,0x10400000,0x10000000,RW_CNB); //bank2
    MMU_SetMTT(0x18000000,0x19f00000,0x18000000,RW_NCNB); //bank3

    MMU_SetMTT(0x40000000,0x40000000,0x40000000,RW_NCNB); //SFR
    MMU_SetMTT(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR
#else

    MMU_SetMTT(0x00000000,0x07f00000,0x00000000,RW_CNB);  //bank0
    MMU_SetMTT(0x08000000,0x0ff00000,0x08000000,RW_CNB);  //bank1
    MMU_SetMTT(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2
    MMU_SetMTT(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3
    MMU_SetMTT(0x20000000,0x27f00000,0x20000000,RW_NCNB); //bank4
    MMU_SetMTT(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5
    MMU_SetMTT(0x30000000,0x30f00000,0x30000000,RW_CB);      //bank6-1
    MMU_SetMTT(0x31000000,0x33e00000,0x31000000,RW_NCNB); //bank6-2
    MMU_SetMTT(0x33f00000,0x33f00000,0x33f00000,RW_CB);   //bank6-3
    MMU_SetMTT(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7

    MMU_SetMTT(0x40000000,0x5af00000,0x40000000,RW_NCNB);//SFR+StepSram
    MMU_SetMTT(0x5b000000,0xfff00000,0x5b000000,RW_FAULT);//not used

#endif


    MMU_SetTTBase(MMUTT_SADDR);
    MMU_SetDomain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR);
    //DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked)
    MMU_SetProcessId(0x0);
    MMU_EnableAlignFault();

    MMU_EnableMMU();
    MMU_EnableICache();
    MMU_EnableDCache(); //DCache should be turned on after MMU is turned on.
}