static void omap2_mcspi_set_slave_mode(struct spi_master *master)
{
u32 l;
l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 1);
mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
omap2_mcspi_ctx[master->bus_num - 1].modulctrl = l;
}
static void omap2_mcspi_set_master_mode(struct spi_device *spi, int single_channel)
{
u32 l;
/* Need reset when switching from slave mode */
l = mcspi_read_reg(spi->master, OMAP2_MCSPI_MODULCTRL);
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, single_channel);
mcspi_write_reg(spi->master, OMAP2_MCSPI_MODULCTRL, l);
}
static void omap2_mcspi_set_master_mode(struct spi_master *master)
{
u32 l;
/* setup when switching from (reset default) slave mode
* to single-channel master mode
*/
l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
}
static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
{
u32 l;
l = mcspi_cached_chconf0(spi);
MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
mcspi_write_chconf0(spi, l);
}
static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
{
u32 l;
l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
MOD_REG_BIT(l, OMAP2_MCSPI_CHCTRL_EN, enable);
mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
}
static void davinci_vcif_stop(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct davinci_vcif_dev *davinci_vcif_dev =
rtd->dai->cpu_dai->private_data;
struct davinci_vc *davinci_vc = davinci_vcif_dev->davinci_vc;
u32 w;
/* Reset transmitter/receiver and sample rate/frame sync generators */
w = readl(davinci_vc->base + DAVINCI_VC_CTRL);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTDAC, 0);
else
MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTADC, 0);
writel(w, davinci_vc->base + DAVINCI_VC_CTRL);
}
static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
{
u32 l;
l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
}
static void omap2_mcspi_set_master_mode(struct spi_master *master)
{
struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
struct omap2_mcspi_regs *ctx = &mcspi->ctx;
u32 l;
/*
* Setup when switching from (reset default) slave mode
* to single-channel master mode
*/
l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
ctx->modulctrl = l;
}
static void davinci_vcif_start(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct davinci_vcif_dev *davinci_vcif_dev =
snd_soc_dai_get_drvdata(rtd->cpu_dai);
struct davinci_vc *davinci_vc = davinci_vcif_dev->davinci_vc;
u32 w;
/* Start the sample generator and enable transmitter/receiver */
w = readl(davinci_vc->base + DAVINCI_VC_CTRL);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTDAC, 0);
else
MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTADC, 0);
writel(w, davinci_vc->base + DAVINCI_VC_CTRL);
}
static void omap2_mcspi_set_master_mode(struct spi_master *master)
{
u32 l;
/* setup when switching from (reset default) slave mode
* to single-channel master mode
*/
l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
#ifdef CONFIG_SPI_SW_CS
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
#else
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 0);
#endif
mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
omap2_mcspi_ctx[master->bus_num - 1].modulctrl = l;
}
static void omap2_mcspi_set_master_mode(struct spi_master *master)
{
u32 l;
struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
/* setup when switching from (reset default) slave mode
* to single-channel master mode based on config value
*/
l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
if (mcspi->force_cs_mode)
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
omap2_mcspi_ctx[master->bus_num - 1].modulctrl = l;
}
static int omap2_mcspi_set_rxfifo(const struct spi_device *spi, int buf_size,
int enable, int bytes_per_wl )
{
u32 l, rw, s;
unsigned short revert = 0;
struct spi_master *master = spi->master;
struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
buf_size = buf_size/bytes_per_wl;
// l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
l = mcspi_cached_chconf0(spi);
s = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
if (enable == 1) {
/* FIFO cannot be enabled for both TX and RX
* simultaneously
*/
// if (l & OMAP2_MCSPI_CHCONF_FFET)
// return -EPERM;
/* Channel needs to be disabled and enabled
* for FIFO setting to take affect
*/
if (s & OMAP2_MCSPI_CHCTRL_EN) {
omap2_mcspi_set_enable(spi, 0);
revert = 1;
}
if (buf_size < mcspi->fifo_depth)
mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL,
((buf_size << 16) |
(buf_size - 1) << 8));
else
mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL,
((buf_size << 16) |
//(mcspi->fifo_depth - 1) << 8));
((mcspi->fifo_depth - 1) << 8) | ((mcspi->fifo_depth - 1) << 0) ));
}
rw = OMAP2_MCSPI_CHCONF_FFER;
MOD_REG_BIT(l, rw, enable);
// mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
mcspi_write_chconf0(spi,l);
if (revert)
omap2_mcspi_set_enable(spi, 1);
return 0;
}
static int omap2_mcspi_set_rxfifo(const struct spi_device *spi, int buf_size,
int wl_bytes, int enable)
{
u32 l, rw, s, xfer_ael;
unsigned short revert = 0;
struct spi_master *master = spi->master;
struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
u32 wcnt = buf_size/wl_bytes;
l = mcspi_cached_chconf0(spi);
s = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
/* Read settings for TX FIFO */
xfer_ael = mcspi_read_reg(master, OMAP2_MCSPI_XFERLEVEL) & 0xff;
if (enable == 1) {
/* Channel needs to be disabled and enabled
* for FIFO setting to take affect
*/
if (s & OMAP2_MCSPI_CHCTRL_EN) {
omap2_mcspi_set_enable(spi, 0);
revert = 1;
}
if (buf_size < mcspi->fifo_depth)
mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL,
((wcnt << 16) |
(buf_size - 1) << 8) |
xfer_ael);
else
mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL,
((wcnt << 16) |
(mcspi->fifo_depth - 1) << 8) |
xfer_ael);
} else {
/* Reset register value for disable case */
mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xfer_ael);
}
rw = OMAP2_MCSPI_CHCONF_FFER;
MOD_REG_BIT(l, rw, enable);
mcspi_write_chconf0(spi, l);
if (revert)
omap2_mcspi_set_enable(spi, 1);
return 0;
}
static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
int is_read, int enable)
{
u32 l, rw;
l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
if (is_read) /* 1 is read, 0 write */
rw = OMAP2_MCSPI_CHCONF_DMAR;
else
rw = OMAP2_MCSPI_CHCONF_DMAW;
MOD_REG_BIT(l, rw, enable);
mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
}
static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
int is_read, int enable)
{
u32 l, rw;
l = mcspi_cached_chconf0(spi);
if (is_read)
rw = OMAP2_MCSPI_CHCONF_DMAR;
else
rw = OMAP2_MCSPI_CHCONF_DMAW;
MOD_REG_BIT(l, rw, enable);
mcspi_write_chconf0(spi, l);
}
static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
{
u32 l;
struct omap2_mcspi* mcspi = spi_master_get_devdata(spi->master);
/* allow GPIOs as chip select if defined */
if (mcspi->cs_gpios && mcspi->cs_gpios[spi->chip_select]) {
int gpio = mcspi->cs_gpios[spi->chip_select];
gpio_set_value(gpio, !cs_active); /* low active */
}
// TXS times out unless we force the CHCONF reg as well
l = mcspi_cached_chconf0(spi);
MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
mcspi_write_chconf0(spi, l);
}
int i2c_slave_write(u_int8_t *buf, int *len)
{
int rc = 0;
int i;
u_int32_t tmp;
i2c_state_t state = SLAVE_IDLE_MODE;
/* printf("%s() Enter: len=%d, status=0x%x\n", __FUNCTION__, *len, REG(I2C_STAT));*/
if (*len < 0) {
printf("%s(): bogus length %d\n", __FUNCTION__, *len);
return(-1);
}
/* check I2C_STAT(I2C_STAT_AAS) to enter slave-transmit-mode from slave-idle-mode */
tmp = poll_i2c_slave_irq(I2C_STAT_AAS | I2C_STAT_SDIR, I2C_SLAVE_XMIT_MAX_TIMEOUT);
if ( !(tmp & I2C_STAT_AAS) || !(tmp & I2C_STAT_SDIR) ) {
// fail to have master-read to slave afer I2C_TIMEOUT time
printf("%s(): not in slave_transmit mode tmp=0x%x\n", __FUNCTION__, tmp);
return(-2);
}
/* enable slave-transmit interrupt */
/* Interrupts must be enabled (except transmit) or I2C module won't work */
tmp = REG(I2C_IE);
MOD_REG_BIT(tmp, I2C_IE_XRDY_IE, 1);
REG(I2C_IE) = tmp;
/* start transmit bytes */
state = SLAVE_XMIT_MODE;
/* transmit 1st byte */
i = 0;
REG(I2C_DXR) = buf[i++];
printf("%s(): send a byte buf[%d]=0x%x\n", __FUNCTION__, 0, buf[0]);
/* transmit rest bytes */
while ( SLAVE_XMIT_MODE == state ) {
/* get I2C_STAT(I2C_STAT_XRDY) to get data or get I2C_STAT(I2C_STAT_SCD)*/
tmp = poll_i2c_slave_irq(I2C_STAT_XRDY | I2C_STAT_NACK | I2C_STAT_SCD, I2C_SLAVE_XMIT_MAX_TIMEOUT);
/*printf("%s(): while status=0x%x\n", __FUNCTION__, tmp);*/
if ( (tmp & I2C_STAT_XRDY) && (i<*len) ) {
printf("%s(): send a byte buf[%d]=0x%x\n", __FUNCTION__, i, buf[i]);
REG(I2C_DXR) = buf[i++];
}
if ( tmp & I2C_STAT_SCD ) {
/* manully clear SCD */
REG(I2C_STAT) |= I2C_STAT_SCD;
printf("%s(): SCD stop-detected status=0x%x\n", __FUNCTION__, REG(I2C_STAT));
/* disable transmit interrupt */
tmp = REG(I2C_IE);
MOD_REG_BIT(tmp, I2C_IE_XRDY_IE, 0);
REG(I2C_IE) = tmp;
/* stop slave-trnasmit */
state = SLAVE_IDLE_MODE;
}
/* special handle to exit slave-transmit mode*/
if ( ( I2C_TIMEOUT == (tmp & I2C_TIMEOUT)) && (i>=*len) ) {
rc = -10; /* fail */
/* stop slave-trnasmit */
state = SLAVE_IDLE_MODE;
}
} /* end of while-loop */
/*printf("%s(): exit rc=%d\n", __FUNCTION__, rc);*/
return(rc);
}
static int davinci_vcif_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct davinci_vcif_dev *davinci_vcif_dev = dai->private_data;
struct davinci_vc *davinci_vc = davinci_vcif_dev->davinci_vc;
struct davinci_pcm_dma_params *dma_params =
&davinci_vcif_dev->dma_params[substream->stream];
u32 w;
/* Restart the codec before setup */
davinci_vcif_stop(substream);
davinci_vcif_start(substream);
/* General line settings */
writel(DAVINCI_VC_CTRL_MASK, davinci_vc->base + DAVINCI_VC_CTRL);
writel(DAVINCI_VC_INT_MASK, davinci_vc->base + DAVINCI_VC_INTCLR);
writel(DAVINCI_VC_INT_MASK, davinci_vc->base + DAVINCI_VC_INTEN);
w = readl(davinci_vc->base + DAVINCI_VC_CTRL);
/* Determine xfer data type */
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_U8:
dma_params->data_type = 0;
MOD_REG_BIT(w, DAVINCI_VC_CTRL_RD_BITS_8 |
DAVINCI_VC_CTRL_RD_UNSIGNED |
DAVINCI_VC_CTRL_WD_BITS_8 |
DAVINCI_VC_CTRL_WD_UNSIGNED, 1);
break;
case SNDRV_PCM_FORMAT_S8:
dma_params->data_type = 1;
MOD_REG_BIT(w, DAVINCI_VC_CTRL_RD_BITS_8 |
DAVINCI_VC_CTRL_WD_BITS_8, 1);
MOD_REG_BIT(w, DAVINCI_VC_CTRL_RD_UNSIGNED |
DAVINCI_VC_CTRL_WD_UNSIGNED, 0);
break;
case SNDRV_PCM_FORMAT_S16_LE:
dma_params->data_type = 2;
MOD_REG_BIT(w, DAVINCI_VC_CTRL_RD_BITS_8 |
DAVINCI_VC_CTRL_RD_UNSIGNED |
DAVINCI_VC_CTRL_WD_BITS_8 |
DAVINCI_VC_CTRL_WD_UNSIGNED, 0);
break;
default:
printk(KERN_WARNING "davinci-vcif: unsupported PCM format");
return -EINVAL;
}
dma_params->acnt = dma_params->data_type;
writel(w, davinci_vc->base + DAVINCI_VC_CTRL);
return 0;
}
