void Conjunct::prefix_print(FILE *output_file, int debug) {
static char dir_glyphs[] = { '-', '?', '+' };
if (debug)
{
Formula::print_head(output_file);
if(pres_debug>=2) fprintf(output_file, "(@%p)", this);
fprintf(output_file, "%s CONJUNCT, ",
exact ? "EXACT" : "INEXACT");
if (simplified) fprintf(output_file, "simplified, ");
if (verified) fprintf(output_file, "verified, ");
if (possible_leading_0s != -1 && guaranteed_leading_0s != -1)
assert (guaranteed_leading_0s <= possible_leading_0s);
if (guaranteed_leading_0s != -1
&& guaranteed_leading_0s == possible_leading_0s)
fprintf(output_file,"# leading 0's = %d,", possible_leading_0s);
else if (possible_leading_0s != -1 || guaranteed_leading_0s != -1) {
if (guaranteed_leading_0s != -1)
fprintf(output_file,"%d <= ",guaranteed_leading_0s);
fprintf(output_file,"#O's");
if (possible_leading_0s != -1)
fprintf(output_file," <= %d",possible_leading_0s);
fprintf(output_file,", ");
}
if (dir_glyphs[leading_dir+1] != '?')
fprintf(output_file," first = %c, ", dir_glyphs[leading_dir+1]);
fprintf(output_file,"myLocals=[");
String s="";
for (Variable_ID_Iterator VI(myLocals); VI; ) {
assert( (*VI)->kind() == Wildcard_Var);
s += (*VI)->name();
print_var_addrs(s, *VI);
VI++;
if(VI) s += ",";
}
s += "] mappedVars=[";
for(Variable_ID_Iterator MVI(mappedVars); MVI; ) {
s += (*MVI)->name();
print_var_addrs(s, *MVI);
MVI++;
if(MVI) s += ",";
}
fprintf(output_file, "%s]\n", (const char *) s);
}
else
level++;
setOutputFile(output_file);
setPrintLevel(level+1);
problem->printProblem(debug);
setPrintLevel(0);
Formula::prefix_print(output_file, debug);
}
/**
* Fudges the MSRs that guest are known to access in some odd cases.
*
* A typical example is a VM that has been moved between different hosts where
* for instance the cpu vendor differs.
*
* @returns VBox status code.
* @param pVM The cross context VM structure.
*/
int cpumR3MsrApplyFudge(PVM pVM)
{
/*
* Basic.
*/
static CPUMMSRRANGE const s_aFudgeMsrs[] =
{
MFO(0x00000000, "IA32_P5_MC_ADDR", Ia32P5McAddr),
MFX(0x00000001, "IA32_P5_MC_TYPE", Ia32P5McType, Ia32P5McType, 0, 0, UINT64_MAX),
MVO(0x00000017, "IA32_PLATFORM_ID", 0),
MFN(0x0000001b, "IA32_APIC_BASE", Ia32ApicBase, Ia32ApicBase),
MVI(0x0000008b, "BIOS_SIGN", 0),
MFX(0x000000fe, "IA32_MTRRCAP", Ia32MtrrCap, ReadOnly, 0x508, 0, 0),
MFX(0x00000179, "IA32_MCG_CAP", Ia32McgCap, ReadOnly, 0x005, 0, 0),
MFX(0x0000017a, "IA32_MCG_STATUS", Ia32McgStatus, Ia32McgStatus, 0, ~(uint64_t)UINT32_MAX, 0),
MFN(0x000001a0, "IA32_MISC_ENABLE", Ia32MiscEnable, Ia32MiscEnable),
MFN(0x000001d9, "IA32_DEBUGCTL", Ia32DebugCtl, Ia32DebugCtl),
MFO(0x000001db, "P6_LAST_BRANCH_FROM_IP", P6LastBranchFromIp),
MFO(0x000001dc, "P6_LAST_BRANCH_TO_IP", P6LastBranchToIp),
MFO(0x000001dd, "P6_LAST_INT_FROM_IP", P6LastIntFromIp),
MFO(0x000001de, "P6_LAST_INT_TO_IP", P6LastIntToIp),
MFS(0x00000277, "IA32_PAT", Ia32Pat, Ia32Pat, Guest.msrPAT),
MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, ~(uint64_t)0xc07),
MFN(0x00000400, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN),
};
int rc = cpumR3MsrApplyFudgeTable(pVM, &s_aFudgeMsrs[0], RT_ELEMENTS(s_aFudgeMsrs));
AssertLogRelRCReturn(rc, rc);
/*
* XP might mistake opterons and other newer CPUs for P4s.
*/
if (pVM->cpum.s.GuestFeatures.uFamily >= 0xf)
{
static CPUMMSRRANGE const s_aP4FudgeMsrs[] =
{
MFX(0x0000002c, "P4_EBC_FREQUENCY_ID", IntelP4EbcFrequencyId, IntelP4EbcFrequencyId, 0xf12010f, UINT64_MAX, 0),
};
rc = cpumR3MsrApplyFudgeTable(pVM, &s_aP4FudgeMsrs[0], RT_ELEMENTS(s_aP4FudgeMsrs));
AssertLogRelRCReturn(rc, rc);
}
return rc;
}
