static void sdram_init(void)
{
int i;
/*
* DDR on CSD0
*/
/* Enable DDR SDRAM operation */
writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC);
/* Set the driving strength */
writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3));
writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5));
writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6));
writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7));
writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8));
/* Initial reset */
writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC);
writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
/* precharge CSD0 all banks */
writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE,
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writel(0x00000000, 0xa0000f00); /* CSD0 precharge address (A10 = 1) */
writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH,
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
for (i = 0; i < 8; i++)
writel(0, 0xa0000f00);
writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE,
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(0xda, 0xa0000033);
writeb(0xff, 0xa1000000);
writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 |
ESDCTL0_BL | ESDCTL0_SMODE_NORMAL,
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
}
void __bare_init __naked barebox_arm_reset_vector(void)
{
uint32_t r;
int i;
arm_cpu_lowlevel_init();
arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8);
/* ahb lite ip interface */
writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0);
writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1);
writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0);
writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1);
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
if (r > 0xa0000000 && r < 0xb0000000)
goto out;
/*
* DDR on CSD0
*/
/* Enable DDR SDRAM operation */
writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC);
/* Set the driving strength */
writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3));
writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5));
writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6));
writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7));
writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8));
/* Initial reset */
writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC);
writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
/* precharge CSD0 all banks */
writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE,
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writel(0x00000000, 0xA0000F00); /* CSD0 precharge address (A10 = 1) */
writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH,
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
for (i = 0; i < 8; i++)
writel(0, 0xa0000f00);
writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE,
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(0xda, 0xa0000033);
writeb(0xff, 0xa1000000);
writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 |
ESDCTL0_BL | ESDCTL0_SMODE_NORMAL,
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND))
imx27_barebox_boot_nand_external(0);
out:
imx27_barebox_entry(NULL);
}