/* Update Flash ROM page table so that it can be written to. */
LOCAL void flashwr_pagetable(BOOL writable)
{
MEMSEG *mp;
UW attr;
mp = MemArea(MSA_FROM, 1);
attr = (writable) ? (PGA_RW | PGA_D | PGA_S) : (mp->pa & 0x000fffff);
ChangeMemAttr(mp->top, mp->end, attr);
return;
}
/*
* set up Flash ROM loading processing
* mode 0 : set up for loading write data
* -1 : set up for writing already loaded data
*
* in the case of setting up loading (mode= 0)
* addr returns the following value.
* addr[0] the start address in RAM area for loading data
* addr[1] the end address in RAM area for loading data
* addr[1] - addr[0] + 1 = load area size
* in principle, load area size matches the size of FLASH ROM.
* But if RAM is small, there may be cases
* in which load area size is smaller than that of Flash ROM size.
* addr[2] the distance between the data load RAM area and Flash ROM area
* adjustment is made so that the addr[0] position is written to the beginning of Flash ROM.
* addr[2] = addr[0] - Flash ROM start address
*
* in the case of setting up for writing (mode = -1),
* we set the writing area based on the addr value when we called this function using mode = 0.
* addr[0] starting address of loaded data in RAM area (to be written)
* addr[1] ending address of loaded data in RAM area (to be written)
* addr[1] - addr[0] + 1 = size of written data
* addr[2] the value remains the same after it was set by mode = 0 (ignored)
* the modified values are returned in addr.
* addr[0] Flash ROM write start address
* addr[1] start address of write data in RAM
* address will be adjusted to the sector boundary of Flash ROM.
* addr[2] number of sectors to write
* Since writing is done in the unit of sectors, the writing will be done from the sector boundary,
* areas immediately before and after the designated area may be part of the write operation.
*/
EXPORT void setupFlashLoad( W mode, UW addr[3] )
{
UW SECMSK = FROM_SECSZ - 1;
UW ofs, sa, romsize, ramtop, ramend;
const MEMSEG *rom, *ram;
/* Flash ROM capacity */
rom = MemArea(MSA_FROM, 1);
romsize = rom->end - rom->top;
/* RAM area for writing */
ram = MemArea(MSA_OS|MSA_WRK, 1);
ramtop = (ram->top + SECMSK) & ~SECMSK;
ramend = ram->end & ~SECMSK;
/* Use the end of RAM area for working area
if we have enough RAM, we set aside the area as large as the last sector */
sa = (ramend - FROM_SECSZ) - romsize;
if ( sa < ramtop ) sa = ramtop;
ofs = sa - (UW)rom->top; /* the distance between the ROM area and RAM work area */
if ( mode >= 0 ) {
/* set up loading */
addr[0] = rom->top + ofs; /* RAM address lower limit */
addr[1] = rom->end + ofs - 1; /* RAM address upper limit */
addr[2] = ofs; /* offset */
if ( addr[1] >= ramend ) addr[1] = ramend - 1;
} else {
/* set up writing */
sa = addr[0] & ~SECMSK; /* RAM start address */
addr[2] = ((addr[1] & ~SECMSK) - sa) / FROM_SECSZ + 1;
/* number of sectors */
addr[1] = sa; /* RAM start address */
addr[0] = sa - ofs; /* ROM start address */
}
}
/*
* display help message for WROM command
*/
LOCAL void prWRomHelp( const HELP *help )
{
const MEMSEG *rom, *ram;
UW ram_top, sz;
rom = MemArea(MSA_FROM, 1);
ram = MemArea(MSA_OS, 1);
if ( rom == NULL || ram == NULL ) {
DSP_S("Not Supported\n");
return;
}
ram_top = (ram->top + FROM_SECSZ - 1) & ~(FROM_SECSZ - 1);
sz = rom->end - rom->top;
if ( sz > ram->end - ram_top ) sz = ram->end - ram_top;
DSP_S(help->msg);
DSP_F5(S," rom_addr : 0x", 08X,rom->top,
S," - 0x", 08X,(rom->end-FROM_SECSZ), CH,'\n');
DSP_F5(S," data_ram_addr : 0x", 08X,ram_top,
S," - 0x", 08X,(ram->end-FROM_SECSZ), CH,'\n');
DSP_F5(S," block_count : 1 - ", D,(sz / FROM_SECSZ),
S," (1 block = ", D,(FROM_SECSZ / 1024), S,"KB)\n");
}
/* basic system set up (performed during reset, and Disk Boot) */
EXPORT void resetSystem(W boot)
{
MEMSEG *mp;
UW i, va;
printk("%s\n", __func__);
return ;
/* obtain DipSw status */
if (!boot) DipSw = DipSwStatus();
DisCacheMMU();
/* set up interrupt controller */
out_w(IT0_IDS0, ~0); /* CPU: all interrupts disabled */
out_w(IT0_IDS1, ~0);
out_w(IT0_IDS2, ~0);
out_w(IT0_IIR, ~0);
out_w(IT3_IPI0_CLR, 0x0000003f);
out_w(IT3_IDS0, ~0); /* DSP: all interrupts disabled */
out_w(IT3_IDS1, ~0);
out_w(IT3_IDS2, ~0);
out_w(IT3_IIR, ~0);
out_w(IT0_IPI3_CLR, 0x0000003f);
out_w(IT0_FID, 0x00000001); /* CPU: FIQ disabled */
out_w(GIO_IIA(GIO_L), 0); /* GPIO: interrupt disabled */
out_w(GIO_IIA(GIO_H), 0);
out_w(GIO_IIA(GIO_HH), 0);
out_w(GIO_IIA(GIO_HHH), 0);
out_w(GIO_GSW(GIO_L), 0); /* GPIO: FIQ interrupt disabled */
out_w(GIO_GSW(GIO_H), 0);
out_w(GIO_GSW(GIO_HH), 0);
out_w(GIO_GSW(GIO_HHH), 0);
out_w(IT0_LIIR, 0x0000000f); /* internal interrupt disabled */
out_w(IT_PINV_CLR0, ~0); /* inhibit interrupt polarity inversion */
out_w(IT_PINV_CLR1, ~0);
out_w(IT_PINV_CLR2, ~0);
out_w(IT0_IEN0, 0x0c000000); /* CPU: GPIO interrupt enabled */
out_w(IT0_IEN1, 0x003c0000);
out_w(IT0_IEN2, 0x00018000);
/* power on controller initialization */
pmicInit();
/* USB power on */
usbPower(TRUE);
/* clear system common area (vector table, and SysInfo) */
memset(&SCInfo, 0, sizeof(SysCommonInfo));
memset(SCArea, 0, sizeof(SysCommonArea));
/* if monitor is loaded into RAM, exclude the RAM area */
mp = MemArea(MSA_OS, 1);
va = (UW)&__loadaddr;
if (va >= mp->top && va < mp->end) mp->end = va;
/* exclude the area where ROM disk data is stored */
va = (UW)ROMInfo->userarea;
if (va >= mp->top && va < mp->end) mp->end = va;
/* initialize system common information (SysInfo) */
SCInfo.ramtop = (void*)mp->top;
if (va < mp->top || va > mp->end) va = mp->end;
SCInfo.ramend = (void*)va;
/* set up EIT vectors */
/* we do not need _defaultHdr absolutely, but just in case set it up */
SCArea->intvec[EIT_DEFAULT] = _defaultHdr; /* default handler */
SCArea->intvec[EIT_UNDEF] = _defaultHdr; /* undefined instruction */
SCArea->intvec[SWI_MONITOR] = _defaultHdr; /* SWI - monitor SVC */
SCArea->intvec[EIT_IRQ(26)] = _gio6Hdr; /* GPIO branch */
SCArea->intvec[EIT_IRQ(27)] = _gio7Hdr;
SCArea->intvec[EIT_IRQ(50)] = _gio0Hdr;
SCArea->intvec[EIT_IRQ(51)] = _gio1Hdr;
SCArea->intvec[EIT_IRQ(52)] = _gio2Hdr;
SCArea->intvec[EIT_IRQ(53)] = _gio3Hdr;
SCArea->intvec[EIT_IRQ(79)] = _gio4Hdr;
SCArea->intvec[EIT_IRQ(80)] = _gio5Hdr;
SCArea->intvec[EIT_IRQ(8)] = _defaultHdr; /* abort switch */
/* set up initial page table */
for (i = 0; i < N_MemSeg; ++i) {
mp = &MemSeg[i];
if (!mp->pa) continue;
/* FlashROM has already been mapped, and so do not touch it */
if (mp->attr == MSA_FROM) continue;
/* set up in unit of section (1MB) */
for ( va = (mp->top & 0xfff00000);
va != ((mp->end + 0x000fffff) & 0xfff00000);
va += 0x00100000 ) {
TopPageTable[va / 0x00100000] =
((mp->pa & 0xfff00000) + va) |
(mp->pa & 0x000fffff);
}
}
for (i = 0; i < N_NoMemSeg; ++i) {
mp = &NoMemSeg[i];
/* set up in unit of section (1MB) */
for ( va = (mp->top & 0xfff00000);
va != ((mp->end + 0x000fffff) & 0xfff00000);
va += 0x00100000 ) {
TopPageTable[va / 0x00100000] = 0;
}
}
DSB();
Asm("mcr p15, 0, %0, cr8, c7, 0":: "r"(0)); /* I/D TLB invalidate */
Asm("mcr p15, 0, %0, cr7, c5, 6":: "r"(0)); /* invalidate BTC */
DSB();
ISB();
EnbCacheMMU();
return;
}
