BOOL MFC_HW_Init(void)
{
/////////////////////////
// //
// 1. Reset the MFC IP //
// //
/////////////////////////
MfcReset();
////////////////////////////////////////
// //
// 2. Download Firmware code into MFC //
// //
////////////////////////////////////////
MfcFirmwareIntoCodeBuf();
MfcFirmwareIntoCodeDownReg();
RETAILMSG(ZONE_FUNCTION, (TEXT("MFC::MFC_HW_Init ::Download FirmwareIntoBitProcessor OK.\r\n")));
////////////////////////////
// //
// 3. Start Bit Processor //
// //
////////////////////////////
MfcStartBitProcessor();
////////////////////////////////////////////////////////////////////
// //
// 4. Set the Base Address Registers for the following 3 buffers //
// (CODE_BUF, WORKING_BUF, PARAMETER_BUF) //
// //
////////////////////////////////////////////////////////////////////
MfcConfigSFR_BITPROC_BUF();
//////////////////////////////////
// //
// 5. Set the Control Registers //
// - STRM_BUF_CTRL //
// - FRME_BUF_CTRL //
// - DEC_FUNC_CTRL //
// - WORK_BUF_CTRL //
// //
//////////////////////////////////
MfcConfigSFR_CTRL_OPTS();
GetFirmwareVersion();
return TRUE;
}
static int s3c_mfc_resume(struct platform_device *pdev)
{
unsigned int dwMfcBase;
int i, index = 0;
MFCInstCtx *mfcinst_ctx;
int inst_no;
int is_mfc_on = 0;
#ifndef CONFIG_PLAT_S5P64XX
unsigned int mfc_pwr, domain_v_ready;
unsigned mfc_clk_val;
unsigned int mfc_clk_temp;
#endif /* CONFIG_PLAT_S5P64XX */
int tmp_openhandle_count;
MFC_Mutex_Lock();
tmp_openhandle_count = _openhandle_count;
#ifdef USE_MFC_DOMAIN_GATING
{
int tmp_openhandle_count = _openhandle_count;
while (tmp_openhandle_count-- > 0)
{
CLOCK_ENABLE;
}
}
#endif /* USE_MFC_DOMAIN_GATING */
#ifndef CONFIG_PLAT_S5P64XX
// mfc clock set 133 Mhz
mfc_clk_val = readl(S3C_CLK_DIV0);
mfc_clk_temp = (mfc_clk_val & (0xF << 28))>>28;
if(mfc_clk_temp == 0)
{ /* MFC clock shouldn't exceed 133MHZ */
mfc_clk_val |= (1<<28);
}
else if(mfc_clk_temp >= 2)
{ /*If MFC clock rate is less than 66MHZ, It is recommended to reset it to 133MHz */
mfc_clk_val = mfc_clk_val & (~(0xF << 28));
mfc_clk_val |= (1<<28);
}
__raw_writel(mfc_clk_val, S3C_CLK_DIV0);
// 1. MFC Power On(Domain V)
mfc_pwr = readl(S3C_NORMAL_CFG);
mfc_pwr |= (1<<9);
__raw_writel(mfc_pwr, S3C_NORMAL_CFG);
// 2. Check MFC power on
do {
domain_v_ready = readl(S3C_BLK_PWR_STAT);
printk("domain v ready : 0x%X\n", domain_v_ready);
msleep(1);
}while(!(domain_v_ready & (1<<1)));
#endif /* CONFIG_PLAT_S5P64XX */
// 3. Firmware download
MfcFirmwareIntoCodeDownReg();
// 4. Power On state
// Validate all the MFC Instances
for (inst_no = 0; inst_no < MFC_NUM_INSTANCES_MAX; inst_no++) {
mfcinst_ctx = MFCInst_GetCtx(inst_no);
if (mfcinst_ctx) {
is_mfc_on = 1;
// When MFC Power On, the MFC instance is validated.
// Then the MFC operations (DEC_EXE, ENC_EXE, etc.) will be performed again
MFCInst_PowerOnState(mfcinst_ctx);
printk(KERN_INFO "MFC_Resume %d-th instance is validated\n", inst_no);
}
}
if (is_mfc_on) {
// 5. Restore MFC SFR
dwMfcBase = (unsigned int)GetMfcSfrVirAddr();
for( i=SAVE_START_ADDR; i<= SAVE_END_ADDR; i+=4 )
{
MFC_WRITE_REG( ( dwMfcBase + i ), mfc_save[index] );
index++;
}
// 6. Command MFC wakeup
MFC_Wakeup();
}
#ifdef USE_MFC_DOMAIN_GATING
if(_openhandle_count == 0) {
DOMAIN_POWER_OFF;
}
#endif /* USE_MFC_DOMAIN_GATING */
MFC_Mutex_Release();
return 0;
}
