int sc_main(int argc, char* argv[])
{
sc_signal<bool> ASig, BSig, FSig;
// a clock that has a positive edge directly a 0 ns
// sc_clock TestClk("TestClock", 10, SC_NS,0.5);
// a clock that has a positive edge only at 10 ns
sc_clock TestClk("TestClock", 10, SC_NS,0.5, 10, SC_NS);
stim Stim1("Stimulus");
Stim1.A(ASig);
Stim1.B(BSig);
Stim1.Clk(TestClk);
exor2 DUT("exor2");
DUT.A(ASig);
DUT.B(BSig);
DUT.F(FSig);
mon Monitor1("Monitor");
Monitor1.A(ASig);
Monitor1.B(BSig);
Monitor1.F(FSig);
Monitor1.Clk(TestClk);
sc_start(); // run forever
return 0;
}
int sc_main(int argc, char* argv[]) {
sc_signal<bool> Din;
sc_signal< sc_uint<4> > r;
sc_clock TestClk("TestClock", 10, SC_NS,0,SC_NS);
stim Stim1("Stimulus");
Stim1.Din(Din);
sr SR1("SR1");
SR1.din(Din);
SR1.clk(TestClk);
SR1.r(r);
mon Monitor1("Monitor");
Monitor1.Din(Din);
Monitor1.r(r);
Monitor1.Clk(TestClk);
sc_start(); // run forever
return 0;
}
int sc_main(int argc, char* argv[]) {
sc_signal<bool> XSig, YSig,ZSig,SSig,CSig;
sc_clock TestClk("TestClock", 10, SC_NS,1,SC_NS);
// sc_trace_file *tf = sc_create_vcd_trace_file("trace");
stim Stim1("Stimulus");
Stim1.X(XSig);
Stim1.Y(YSig);
Stim1.Z(ZSig);
Stim1.Clk(TestClk);
adder A1("A");
A1.a(XSig);
A1.b(YSig);
A1.c(ZSig);
A1.carry(CSig);
A1.sum(SSig);
/*
sc_trace(tf,XSig,"X");
sc_trace(tf,YSig,"Y");
sc_trace(tf,ZSig,"Z");
sc_trace(tf,SSig,"S");
sc_trace(tf,CSig,"C");
*/
mon Monitor1("Monitor");
Monitor1.X(XSig);
Monitor1.Y(YSig);
Monitor1.Z(ZSig);
Monitor1.S(SSig);
Monitor1.C(CSig);
Monitor1.Clk(TestClk);
// sc_close_vcd_trace_file(tf);
sc_start(); // run forever
return 0;
}
int sc_main(int argc, char* argv[]) {
sc_signal<bool> Write;
sc_signal < sc_uint<5> > rdAddrA,rdAddrB,wrAddr;
sc_signal < sc_uint<32> > rdDataA,rdDataB,wrData;
sc_clock TestClk("TestClock", 10, SC_NS,0,SC_NS);
stim Stim1("Stimulus");
Stim1.write(Write);
Stim1.rdAddrA(rdAddrA);
Stim1.rdAddrB(rdAddrB);
Stim1.wrAddr(wrAddr);
Stim1.wrData(wrData);
rf RF1("SR1");
RF1.write(Write);
RF1.clk(TestClk);
RF1.rdAddrA(rdAddrA);
RF1.rdAddrB(rdAddrB);
RF1.wrAddr(wrAddr);
RF1.rdDataA(rdDataA);
RF1.rdDataB(rdDataB);
RF1.wrData(wrData);
mon Monitor1("Monitor");
Monitor1.Clk(TestClk);
Monitor1.write(Write);
Monitor1.rdAddrA(rdAddrA);
Monitor1.rdAddrB(rdAddrB);
Monitor1.wrAddr(wrAddr);
Monitor1.rdDataA(rdDataA);
Monitor1.rdDataB(rdDataB);
Monitor1.wrData(wrData);
sc_start(); // run forever
return 0;
}
int sc_main(int argc, char* argv[]) {
sc_signal<bool>A1Sig, A2Sig, B1Sig, B2Sig, CinSig, S1Sig, S2Sig, CoSig;
sc_clock TestClk("TestClock", 10, SC_NS, 0.5);
stim Stim1("Stimulus");
Stim1.A1(A1Sig);
Stim1.A2(A2Sig);
Stim1.B1(B1Sig);
Stim1.B2(B2Sig);
Stim1.Cin(CinSig);
Stim1.Clk(TestClk);
adder2 DUT("adder2");
DUT.A1(A1Sig);
DUT.A2(A2Sig);
DUT.B1(B1Sig);
DUT.B2(B2Sig);
DUT.Cin(CinSig);
DUT.Sum1(S1Sig);
DUT.Sum2(S2Sig);
DUT.Cout(CoSig);
mon Monitor1("Monitor");
Monitor1.A1(A1Sig);
Monitor1.A2(A2Sig);
Monitor1.B1(B1Sig);
Monitor1.B2(B2Sig);
Monitor1.Cin(CinSig);
Monitor1.Sum1(S1Sig);
Monitor1.Sum2(S2Sig);
Monitor1.Cout(CoSig);
Monitor1.Clk(TestClk);
sc_start();
return 0;
}
