static void rLB_ReadPage(U32 addr, unsigned char * to) { U32 i; rNF_Reset(); // Enable the chip NF_nFCE_L(); NF_CLEAR_RB(); // Issue Read command NF_CMD(CMD_READ); // Set up address NF_ADDR(0x00); NF_ADDR(0x00); NF_ADDR((addr) & 0xff); NF_ADDR((addr >> 8) & 0xff); NF_ADDR((addr >> 16) & 0xff); NF_CMD(CMD_READ3); NF_DETECT_RB(); // wait tR(max 12us) for (i = 0; i < 2048; i++) { to[i] = NF_RDDATA8(); } NF_nFCE_H(); }
// int printk(const char *fmt, ...); void __low_nand_reset() { NF_CE_L(); NF_CLEAR_RB(); NF_CMD(CMD_RESET); NF_DETECT_RB(); NF_CE_H(); }
// // Reset the chip // static void rNF_Reset() { NF_CE_L(); NF_CLEAR_RB(); NF_CMD(CMD_RESET); NF_DETECT_RB(); NF_CE_H(); }
char __low_nand_write_page(unsigned int page_addr,unsigned char *from) { U32 i; char nfstatus; unsigned int *pfrom = (unsigned int *)from;//2440的NFADDR寄存器是32位的 // printk("write page addr :%.8x \r\n",page_addr); // __low_nand_reset(); // Enable the chip NF_nFCE_L(); NF_CLEAR_RB(); // Issue Read command NF_CMD(CMD_WRITE1); // Set up address NF_ADDR(page_addr & 0xff); NF_ADDR((page_addr >> 8) & 0x0f); NF_ADDR((page_addr >> 12) & 0xff); NF_ADDR((page_addr >> 20) & 0xff); NF_ADDR((page_addr >> 28) & 0x01); // NF_WRDATA(0xffffffff); // NF_WRDATA(0xffffffff); // NF_WRDATA(0xffffffff); // NF_WRDATA(0xffffffff); for(i = 0;i < (NAND_PAGE_SIZE+64) >> 2;++i) { NF_WRDATA( *((unsigned*)pfrom++)); } NF_CMD(CMD_WRITE2); NF_DETECT_RB(); // wait tR(max 12us) NF_CMD(CMD_STATUS); return (NF_RDDATA8() & 0x01); // nfstatus = NF_RDDATA8(); // NF_nFCE_H(); // printk("nand status:%x\r\n",nfstatus); }
char __low_nand_erase_block(unsigned int row_addr) { NF_nFCE_L(); NF_CLEAR_RB(); NF_CMD(CMD_ERASE1); NF_ADDR((row_addr >> 12) & 0xff); NF_ADDR((row_addr >> 20) & 0xff); NF_ADDR((row_addr >> 28) & 0x01); NF_CMD(CMD_ERASE2); NF_DETECT_RB(); NF_CMD(CMD_STATUS); return (NF_RDDATA8() & 0x01); }
void SubmitSpareAreaReadCmd(DWORD SectorStartAddr, DWORD SpareStartAddr) { NF_nFCE_L(); NF_CLEAR_RB(); NF_CMD(CMD_READ); // Send read command. NF_ADDR((SpareStartAddr)&0xff); NF_ADDR((SpareStartAddr>>8)&0xff); NF_ADDR((SectorStartAddr) & 0xff); NF_ADDR((SectorStartAddr >> 8) & 0xff); if(g_bNeedExtAddr) { NF_ADDR((SectorStartAddr >> 16) & 0xff); } NF_CMD(CMD_READ3); // 2nd command NF_DETECT_RB(); // Wait for command to complete. }
void __low_nand_read_page(unsigned int page_addr,unsigned char *to) { U32 i; char nfstatus; unsigned int *pto = (unsigned int *)to; // printk("read page addr :%.8x \r\n",page_addr); // __low_nand_reset(); // Enable the chip NF_nFCE_L(); NF_CLEAR_RB(); // Issue Read command NF_CMD(CMD_READ); // Set up address NF_ADDR(page_addr & 0xff); NF_ADDR((page_addr >> 8) & 0x0f); NF_ADDR((page_addr >> 12) & 0xff); NF_ADDR((page_addr >> 20) & 0xff); NF_ADDR((page_addr >> 28) & 0x01); NF_CMD(CMD_READ2); NF_DETECT_RB(); // wait tR(max 12us) for (i = 0; i < (NAND_PAGE_SIZE+64) >> 2;++i) { *((unsigned*)pto++) = NF_RDDATA(); } // for (i = 0; i < NAND_PAGE_SIZE ;++i) // { // to[i] = NF_RDDATA8(); // } NF_nFCE_H(); }