static void noc_set_qos_mode(struct msm_bus_noc_info *ninfo, uint32_t mport, uint8_t mode, uint8_t perm_mode) { if (mode < NOC_QOS_MODE_MAX && ((1 << mode) & perm_mode)) { uint32_t reg_val; reg_val = readl_relaxed(NOC_QOS_MODEn_ADDR(ninfo->base, mport)) & NOC_QOS_MODEn_RMSK; writel_relaxed(((reg_val & (~(NOC_QOS_MODEn_MODE_BMSK))) | (mode & NOC_QOS_MODEn_MODE_BMSK)), NOC_QOS_MODEn_ADDR(ninfo->base, mport)); } /* Ensure qos mode is set before exiting */ wmb(); }
static void noc_set_qos_mode(struct msm_bus_noc_info *ninfo, uint32_t mport, uint8_t mode) { if (mode < NOC_QOS_MODE_MAX && ((1 << mode) & ninfo->mas_modes[mport])) { uint32_t reg_val; reg_val = readl_relaxed(NOC_QOS_MODEn_ADDR(ninfo->base, mport)) & NOC_QOS_MODEn_RMSK; writel_relaxed(((reg_val & (~(NOC_QOS_MODEn_MODE_BMSK))) | (mode & NOC_QOS_MODEn_MODE_BMSK)), NOC_QOS_MODEn_ADDR(ninfo->base, mport)); } wmb(); }
static void noc_set_qos_mode(void __iomem *base, uint32_t qos_off, uint32_t mport, uint32_t qos_delta, uint8_t mode, uint8_t perm_mode) { if (mode < NOC_QOS_MODE_MAX && ((1 << mode) & perm_mode)) { uint32_t reg_val; reg_val = readl_relaxed(NOC_QOS_MODEn_ADDR(base, qos_off, mport, qos_delta)) & NOC_QOS_MODEn_RMSK; writel_relaxed(((reg_val & (~(NOC_QOS_MODEn_MODE_BMSK))) | (mode & NOC_QOS_MODEn_MODE_BMSK)), NOC_QOS_MODEn_ADDR(base, qos_off, mport, qos_delta)); } /* Ensure qos mode is set before exiting */ wmb(); }
uint8_t msm_bus_noc_get_qos_mode(struct msm_bus_noc_info *ninfo, uint32_t mport, uint32_t mode, uint32_t perm_mode) { if (NOC_QOS_MODES_ALL_PERM == perm_mode) return readl_relaxed(NOC_QOS_MODEn_ADDR(ninfo->base, mport)) & NOC_QOS_MODEn_MODE_BMSK; else return 31 - __CLZ(mode & NOC_QOS_MODES_ALL_PERM); }
uint8_t msm_bus_noc_get_qos_mode(void __iomem *base, uint32_t qos_off, uint32_t mport, uint32_t qos_delta, uint32_t mode, uint32_t perm_mode) { if (NOC_QOS_MODES_ALL_PERM == perm_mode) return readl_relaxed(NOC_QOS_MODEn_ADDR(base, qos_off, mport, qos_delta)) & NOC_QOS_MODEn_MODE_BMSK; else return 31 - __CLZ(mode & NOC_QOS_MODES_ALL_PERM); }
static void msm_bus_noc_set_qos_bw(struct msm_bus_noc_info *ninfo, uint32_t mport, uint8_t perm_mode, struct msm_bus_noc_qos_bw *qbw) { uint32_t reg_val, val, mode; if (!ninfo->qos_freq) { MSM_BUS_DBG("Zero QoS Freq\n"); return; } /* If Limiter or Regulator modes are not supported, bw not available*/ if (perm_mode & (NOC_QOS_PERM_MODE_LIMITER | NOC_QOS_PERM_MODE_REGULATOR)) { uint32_t bw_val = noc_bw_field(qbw->bw, ninfo->qos_freq); uint32_t sat_val = noc_sat_field(qbw->bw, qbw->ws, ninfo->qos_freq); MSM_BUS_DBG("NOC: BW: perm_mode: %d bw_val: %d, sat_val: %d\n", perm_mode, bw_val, sat_val); /* * If in Limiter/Regulator mode, first go to fixed mode. * Clear QoS accumulator **/ mode = readl_relaxed(NOC_QOS_MODEn_ADDR(ninfo->base, mport)) & NOC_QOS_MODEn_MODE_BMSK; if (mode == NOC_QOS_MODE_REGULATOR || mode == NOC_QOS_MODE_LIMITER) { reg_val = readl_relaxed(NOC_QOS_MODEn_ADDR(ninfo-> base, mport)); val = NOC_QOS_MODE_FIXED; writel_relaxed((reg_val & (~(NOC_QOS_MODEn_MODE_BMSK))) | (val & NOC_QOS_MODEn_MODE_BMSK), NOC_QOS_MODEn_ADDR(ninfo->base, mport)); } reg_val = readl_relaxed(NOC_QOS_BWn_ADDR(ninfo->base, mport)); val = bw_val << NOC_QOS_BWn_BW_SHFT; writel_relaxed(((reg_val & (~(NOC_QOS_BWn_BW_BMSK))) | (val & NOC_QOS_BWn_BW_BMSK)), NOC_QOS_BWn_ADDR(ninfo->base, mport)); MSM_BUS_DBG("NOC: BW: Wrote value: 0x%x\n", ((reg_val & (~NOC_QOS_BWn_BW_BMSK)) | (val & NOC_QOS_BWn_BW_BMSK))); reg_val = readl_relaxed(NOC_QOS_SATn_ADDR(ninfo->base, mport)); val = sat_val << NOC_QOS_SATn_SAT_SHFT; writel_relaxed(((reg_val & (~(NOC_QOS_SATn_SAT_BMSK))) | (val & NOC_QOS_SATn_SAT_BMSK)), NOC_QOS_SATn_ADDR(ninfo->base, mport)); MSM_BUS_DBG("NOC: SAT: Wrote value: 0x%x\n", ((reg_val & (~NOC_QOS_SATn_SAT_BMSK)) | (val & NOC_QOS_SATn_SAT_BMSK))); /* Set mode back to what it was initially */ reg_val = readl_relaxed(NOC_QOS_MODEn_ADDR(ninfo->base, mport)); writel_relaxed((reg_val & (~(NOC_QOS_MODEn_MODE_BMSK))) | (mode & NOC_QOS_MODEn_MODE_BMSK), NOC_QOS_MODEn_ADDR(ninfo->base, mport)); /* Ensure that all writes for bandwidth registers have * completed before returning */ wmb(); } }
static void msm_bus_noc_set_qos_bw(struct msm_bus_noc_info *ninfo, uint32_t mport, uint8_t perm_mode, struct msm_bus_noc_qos_bw *qbw) { uint32_t reg_val, val, mode; if (!ninfo->qos_freq) { MSM_BUS_DBG("Zero QoS Freq\n"); return; } if (perm_mode & (NOC_QOS_PERM_MODE_LIMITER | NOC_QOS_PERM_MODE_REGULATOR)) { uint32_t bw_val = noc_bw_field(qbw->bw, ninfo->qos_freq); uint32_t sat_val = noc_sat_field(qbw->bw, qbw->ws, ninfo->qos_freq); MSM_BUS_DBG("NOC: BW: perm_mode: %d bw_val: %d, sat_val: %d\n", perm_mode, bw_val, sat_val); mode = readl_relaxed(NOC_QOS_MODEn_ADDR(ninfo->base, mport)) & NOC_QOS_MODEn_MODE_BMSK; if (mode == NOC_QOS_MODE_REGULATOR || mode == NOC_QOS_MODE_LIMITER) { reg_val = readl_relaxed(NOC_QOS_MODEn_ADDR(ninfo-> base, mport)); val = NOC_QOS_MODE_FIXED; writel_relaxed((reg_val & (~(NOC_QOS_MODEn_MODE_BMSK))) | (val & NOC_QOS_MODEn_MODE_BMSK), NOC_QOS_MODEn_ADDR(ninfo->base, mport)); } reg_val = readl_relaxed(NOC_QOS_BWn_ADDR(ninfo->base, mport)); val = bw_val << NOC_QOS_BWn_BW_SHFT; writel_relaxed(((reg_val & (~(NOC_QOS_BWn_BW_BMSK))) | (val & NOC_QOS_BWn_BW_BMSK)), NOC_QOS_BWn_ADDR(ninfo->base, mport)); MSM_BUS_DBG("NOC: BW: Wrote value: 0x%x\n", ((reg_val & (~NOC_QOS_BWn_BW_BMSK)) | (val & NOC_QOS_BWn_BW_BMSK))); reg_val = readl_relaxed(NOC_QOS_SATn_ADDR(ninfo->base, mport)); val = sat_val << NOC_QOS_SATn_SAT_SHFT; writel_relaxed(((reg_val & (~(NOC_QOS_SATn_SAT_BMSK))) | (val & NOC_QOS_SATn_SAT_BMSK)), NOC_QOS_SATn_ADDR(ninfo->base, mport)); MSM_BUS_DBG("NOC: SAT: Wrote value: 0x%x\n", ((reg_val & (~NOC_QOS_SATn_SAT_BMSK)) | (val & NOC_QOS_SATn_SAT_BMSK))); reg_val = readl_relaxed(NOC_QOS_MODEn_ADDR(ninfo->base, mport)); writel_relaxed((reg_val & (~(NOC_QOS_MODEn_MODE_BMSK))) | (mode & NOC_QOS_MODEn_MODE_BMSK), NOC_QOS_MODEn_ADDR(ninfo->base, mport)); wmb(); } }