static void __init pci_fixup_ioc3(struct pci_dev *d) { unsigned long bus_id = (unsigned) d->bus->number; printk("PCI: Fixing base addresses for IOC3 device %s\n", d->slot_name); d->resource[0].start |= NODE_OFFSET(bus_to_nid[bus_id]); d->resource[0].end |= NODE_OFFSET(bus_to_nid[bus_id]); pci_disable_swapping(d); }
int bridge_probe(nasid_t nasid, int widget_id, int masterwid) { unsigned long offset = NODE_OFFSET(nasid); struct bridge_controller *bc; static int num_bridges = 0; bridge_t *bridge; int slot; pci_set_flags(PCI_PROBE_ONLY); printk("a bridge\n"); /* XXX: kludge alert.. */ if (!num_bridges) ioport_resource.end = ~0UL; bc = &bridges[num_bridges]; bc->pc.pci_ops = &bridge_pci_ops; bc->pc.mem_resource = &bc->mem; bc->pc.io_resource = &bc->io; bc->pc.index = num_bridges; bc->mem.name = "Bridge PCI MEM"; bc->pc.mem_offset = offset; bc->mem.start = 0; bc->mem.end = ~0UL; bc->mem.flags = IORESOURCE_MEM; bc->io.name = "Bridge IO MEM"; bc->pc.io_offset = offset; bc->io.start = 0UL; bc->io.end = ~0UL; bc->io.flags = IORESOURCE_IO; bc->irq_cpu = smp_processor_id(); bc->widget_id = widget_id; bc->nasid = nasid; bc->baddr = (u64)masterwid << 60 | PCI64_ATTR_BAR; /* * point to this bridge */ bridge = (bridge_t *) RAW_NODE_SWIN_BASE(nasid, widget_id); /* * Clear all pending interrupts. */ bridge->b_int_rst_stat = BRIDGE_IRR_ALL_CLR; /* * Until otherwise set up, assume all interrupts are from slot 0 */ bridge->b_int_device = 0x0; /* * swap pio's to pci mem and io space (big windows) */ bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP | BRIDGE_CTRL_MEM_SWAP; #ifdef CONFIG_PAGE_SIZE_4KB bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE; #else /* 16kB or larger */ bridge->b_wid_control |= BRIDGE_CTRL_PAGE_SIZE; #endif /* * Hmm... IRIX sets additional bits in the address which * are documented as reserved in the bridge docs. */ bridge->b_wid_int_upper = 0x8000 | (masterwid << 16); bridge->b_wid_int_lower = 0x01800090; /* PI_INT_PEND_MOD off*/ bridge->b_dir_map = (masterwid << 20); /* DMA */ bridge->b_int_enable = 0; for (slot = 0; slot < 8; slot ++) { bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR; bc->pci_int[slot] = -1; } bridge->b_wid_tflush; /* wait until Bridge PIO complete */ bc->base = bridge; register_pci_controller(&bc->pc); num_bridges++; return 0; }
int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid) { unsigned long offset = NODE_OFFSET(nasid); struct bridge_controller *bc; static int num_bridges = 0; bridge_t *bridge; int slot; pci_set_flags(PCI_PROBE_ONLY); printk("a bridge\n"); /* */ if (!num_bridges) ioport_resource.end = ~0UL; bc = &bridges[num_bridges]; bc->pc.pci_ops = &bridge_pci_ops; bc->pc.mem_resource = &bc->mem; bc->pc.io_resource = &bc->io; bc->pc.index = num_bridges; bc->mem.name = "Bridge PCI MEM"; bc->pc.mem_offset = offset; bc->mem.start = 0; bc->mem.end = ~0UL; bc->mem.flags = IORESOURCE_MEM; bc->io.name = "Bridge IO MEM"; bc->pc.io_offset = offset; bc->io.start = 0UL; bc->io.end = ~0UL; bc->io.flags = IORESOURCE_IO; bc->irq_cpu = smp_processor_id(); bc->widget_id = widget_id; bc->nasid = nasid; bc->baddr = (u64)masterwid << 60 | PCI64_ATTR_BAR; /* */ bridge = (bridge_t *) RAW_NODE_SWIN_BASE(nasid, widget_id); /* */ bridge->b_int_rst_stat = BRIDGE_IRR_ALL_CLR; /* */ bridge->b_int_device = 0x0; /* */ bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP | BRIDGE_CTRL_MEM_SWAP; #ifdef CONFIG_PAGE_SIZE_4KB bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE; #else /* */ bridge->b_wid_control |= BRIDGE_CTRL_PAGE_SIZE; #endif /* */ bridge->b_wid_int_upper = 0x8000 | (masterwid << 16); bridge->b_wid_int_lower = 0x01800090; /* */ bridge->b_dir_map = (masterwid << 20); /* */ bridge->b_int_enable = 0; for (slot = 0; slot < 8; slot ++) { bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR; bc->pci_int[slot] = -1; } bridge->b_wid_tflush; /* */ bc->base = bridge; register_pci_controller(&bc->pc); num_bridges++; return 0; }