VOID BSP_QSpiInit(UINT16 SpiClkDiv) { // SPIpins can't used as GPIO NST_WR_PWM_REG(ADDR_GPIO_PIN_MUX_CTRL, NST_RD_PWM_REG(ADDR_GPIO_PIN_MUX_CTRL) & (~ENA_QSPIM_GPIO)); NST_QSPI->SSIENR= 0x00; NST_QSPI->IMR= 0x00; //NST_QSPI->DMACR= 0x00; //NST_QSPI->DMATDLR= 0x00; NST_QSPI->BAUDR= SpiClkDiv; NST_QSPI->CTRLR0= (QSPI_TMOD_TR << QSPI_TMOD_OFFSET) | (QSPI_FRF_QSPI << QSPI_FRF_OFFSET) |(QSPI_FRM_SIZE - 1) |( QSPI_MODE_3 << 6); NST_QSPI->CTRLR1= 0x00; //NST_QSPI->SER= 0x01; NST_QSPI->SSIENR= 0x01; }
void GPIO_Init(GPIO_InitTypeDef* GPIO_InitStruct) { int pin_reg = 0,mode_reg; /* Check the parameters */ assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); /* set ADDR_GPIO_PIN_MUX_CTRL Register*/ pin_reg = NST_RD_PWM_REG(ADDR_GPIO_PIN_MUX_CTRL); pin_reg |= GPIO_InitStruct->GPIO_Pin; /* set SWPORTA_DDR Register*/ mode_reg = NST_RD_GPIO_REG(SWPORTA_DDR); if(GPIO_InitStruct->GPIO_Mode){ mode_reg |= GPIO_InitStruct->GPIO_Pin; } else { mode_reg &= ~GPIO_InitStruct->GPIO_Pin; } NST_WR_PWM_REG(ADDR_GPIO_PIN_MUX_CTRL, pin_reg); NST_WR_GPIO_REG(SWPORTA_DDR, mode_reg); }