<<<<<<< HEAD nv40_fb_set_tile_region(struct drm_device *dev, int i) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; switch (dev_priv->chipset) { case 0x40: nv_wr32(dev, NV10_PFB_TLIMIT(i), tile->limit); nv_wr32(dev, NV10_PFB_TSIZE(i), tile->pitch); nv_wr32(dev, NV10_PFB_TILE(i), tile->addr); break; default: nv_wr32(dev, NV40_PFB_TLIMIT(i), tile->limit); nv_wr32(dev, NV40_PFB_TSIZE(i), tile->pitch); nv_wr32(dev, NV40_PFB_TILE(i), tile->addr); ======= nv40_fb_set_region_tiling(struct drm_device *dev, int i, uint32_t addr, uint32_t size, uint32_t pitch) { struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t limit = max(1u, addr + size) - 1; if (pitch) addr |= 1; switch (dev_priv->chipset) { case 0x40: nv_wr32(dev, NV10_PFB_TLIMIT(i), limit); nv_wr32(dev, NV10_PFB_TSIZE(i), pitch); nv_wr32(dev, NV10_PFB_TILE(i), addr); break; default: nv_wr32(dev, NV40_PFB_TLIMIT(i), limit); nv_wr32(dev, NV40_PFB_TSIZE(i), pitch); nv_wr32(dev, NV40_PFB_TILE(i), addr); >>>>>>> 296c66da8a02d52243f45b80521febece5ed498a break; } }
void nv20_fb_set_tile_region(struct drm_device *dev, int i) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; nv_wr32(dev, NV10_PFB_TLIMIT(i), tile->limit); nv_wr32(dev, NV10_PFB_TSIZE(i), tile->pitch); nv_wr32(dev, NV10_PFB_TILE(i), tile->addr); nv_wr32(dev, NV20_PFB_ZCOMP(i), tile->zcomp); }
void nv10_fb_set_region_tiling(struct drm_device *dev, int i, uint32_t addr, uint32_t size, uint32_t pitch) { struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t limit = max(1u, addr + size) - 1; if (pitch) { if (dev_priv->card_type >= NV_20) addr |= 1; else addr |= 1 << 31; } nv_wr32(dev, NV10_PFB_TLIMIT(i), limit); nv_wr32(dev, NV10_PFB_TSIZE(i), pitch); nv_wr32(dev, NV10_PFB_TILE(i), addr); }
int nv30_graph_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; // uint32_t vramsz, tmp; int ret, i; NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH); NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | NV_PMC_ENABLE_PGRAPH); /* Create Context Pointer Table */ dev_priv->ctx_table_size = 32 * 4; if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, dev_priv->ctx_table_size, 16, NVOBJ_FLAG_ZERO_ALLOC, &dev_priv->ctx_table))) return ret; NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_TABLE, dev_priv->ctx_table->instance >> 4); NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF); NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000); NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x401287c0); NV_WRITE(0x400890, 0x01b463ff); NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xf2de0475); NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00008000); NV_WRITE(NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); NV_WRITE(0x400B80, 0x1003d888); NV_WRITE(0x400B84, 0x0c000000); NV_WRITE(0x400098, 0x00000000); NV_WRITE(0x40009C, 0x0005ad00); NV_WRITE(0x400B88, 0x62ff00ff); // suspiciously like PGRAPH_DEBUG_2 NV_WRITE(0x4000a0, 0x00000000); NV_WRITE(0x4000a4, 0x00000008); NV_WRITE(0x4008a8, 0xb784a400); NV_WRITE(0x400ba0, 0x002f8685); NV_WRITE(0x400ba4, 0x00231f3f); NV_WRITE(0x4008a4, 0x40000020); if (dev_priv->chipset == 0x34) { NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0004); NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00200201); NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0008); NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000008); NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0000); NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000032); NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E00004); NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000002); } NV_WRITE(0x4000c0, 0x00000016); /* copy tile info from PFB */ for (i = 0; i < NV10_PFB_TILE__SIZE; i++) { NV_WRITE(0x00400904 + i*0x10, NV_READ(NV10_PFB_TLIMIT(i))); /* which is NV40_PGRAPH_TLIMIT0(i) ?? */ NV_WRITE(0x00400908 + i*0x10, NV_READ(NV10_PFB_TSIZE(i))); /* which is NV40_PGRAPH_TSIZE0(i) ?? */ NV_WRITE(0x00400900 + i*0x10, NV_READ(NV10_PFB_TILE(i))); /* which is NV40_PGRAPH_TILE0(i) ?? */ } NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10000100); NV_WRITE(NV10_PGRAPH_STATE , 0xFFFFFFFF); NV_WRITE(0x0040075c , 0x00000001); NV_WRITE(NV04_PGRAPH_FIFO , 0x00000001); /* begin RAM config */ // vramsz = drm_get_resource_len(dev, 0) - 1; NV_WRITE(0x4009A4, NV_READ(NV04_PFB_CFG0)); NV_WRITE(0x4009A8, NV_READ(NV04_PFB_CFG1)); if (dev_priv->chipset != 0x34) { NV_WRITE(0x400750, 0x00EA0000); NV_WRITE(0x400754, NV_READ(NV04_PFB_CFG0)); NV_WRITE(0x400750, 0x00EA0004); NV_WRITE(0x400754, NV_READ(NV04_PFB_CFG1)); } #if 0 NV_WRITE(0x400820, 0); NV_WRITE(0x400824, 0); NV_WRITE(0x400864, vramsz-1); NV_WRITE(0x400868, vramsz-1); NV_WRITE(0x400B20, 0x00000000); NV_WRITE(0x400B04, 0xFFFFFFFF); /* per-context state, doesn't belong here */ tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00; NV_WRITE(NV10_PGRAPH_SURFACE, tmp); tmp = NV_READ(NV10_PGRAPH_SURFACE) | 0x00020100; NV_WRITE(NV10_PGRAPH_SURFACE, tmp); NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMIN, 0); NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMIN, 0); NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff); NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff); #endif return 0; }
int nv20_graph_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = (struct drm_nouveau_private *)dev->dev_private; uint32_t tmp, vramsz; int ret, i; NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH); NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | NV_PMC_ENABLE_PGRAPH); /* Create Context Pointer Table */ dev_priv->ctx_table_size = 32 * 4; if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, dev_priv->ctx_table_size, 16, NVOBJ_FLAG_ZERO_ALLOC, &dev_priv->ctx_table))) return ret; NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_TABLE, dev_priv->ctx_table->instance >> 4); nv20_graph_rdi(dev); NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF); NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000); NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x00118700); NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */ NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00000000); NV_WRITE(0x40009C , 0x00000040); if (dev_priv->chipset >= 0x25) { NV_WRITE(0x400890, 0x00080000); NV_WRITE(0x400610, 0x304B1FB6); NV_WRITE(0x400B80, 0x18B82880); NV_WRITE(0x400B84, 0x44000000); NV_WRITE(0x400098, 0x40000080); NV_WRITE(0x400B88, 0x000000ff); } else { NV_WRITE(0x400880, 0x00080000); /* 0x0008c7df */ NV_WRITE(0x400094, 0x00000005); NV_WRITE(0x400B80, 0x45CAA208); /* 0x45eae20e */ NV_WRITE(0x400B84, 0x24000000); NV_WRITE(0x400098, 0x00000040); NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E00038); NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000030); NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E10038); NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000030); } /* copy tile info from PFB */ for (i = 0; i < NV10_PFB_TILE__SIZE; i++) { NV_WRITE(0x00400904 + i*0x10, NV_READ(NV10_PFB_TLIMIT(i))); /* which is NV40_PGRAPH_TLIMIT0(i) ?? */ NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0030+i*4); NV_WRITE(NV10_PGRAPH_RDI_DATA, NV_READ(NV10_PFB_TLIMIT(i))); NV_WRITE(0x00400908 + i*0x10, NV_READ(NV10_PFB_TSIZE(i))); /* which is NV40_PGRAPH_TSIZE0(i) ?? */ NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0050+i*4); NV_WRITE(NV10_PGRAPH_RDI_DATA, NV_READ(NV10_PFB_TSIZE(i))); NV_WRITE(0x00400900 + i*0x10, NV_READ(NV10_PFB_TILE(i))); /* which is NV40_PGRAPH_TILE0(i) ?? */ NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0010+i*4); NV_WRITE(NV10_PGRAPH_RDI_DATA, NV_READ(NV10_PFB_TILE(i))); } for (i = 0; i < 8; i++) { NV_WRITE(0x400980+i*4, NV_READ(0x100300+i*4)); NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0090+i*4); NV_WRITE(NV10_PGRAPH_RDI_DATA, NV_READ(0x100300+i*4)); } NV_WRITE(0x4009a0, NV_READ(0x100324)); NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA000C); NV_WRITE(NV10_PGRAPH_RDI_DATA, NV_READ(0x100324)); NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10000100); NV_WRITE(NV10_PGRAPH_STATE , 0xFFFFFFFF); NV_WRITE(NV04_PGRAPH_FIFO , 0x00000001); tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00; NV_WRITE(NV10_PGRAPH_SURFACE, tmp); tmp = NV_READ(NV10_PGRAPH_SURFACE) | 0x00020100; NV_WRITE(NV10_PGRAPH_SURFACE, tmp); /* begin RAM config */ vramsz = drm_get_resource_len(dev, 0) - 1; NV_WRITE(0x4009A4, NV_READ(NV04_PFB_CFG0)); NV_WRITE(0x4009A8, NV_READ(NV04_PFB_CFG1)); NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0000); NV_WRITE(NV10_PGRAPH_RDI_DATA , NV_READ(NV04_PFB_CFG0)); NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0004); NV_WRITE(NV10_PGRAPH_RDI_DATA , NV_READ(NV04_PFB_CFG1)); NV_WRITE(0x400820, 0); NV_WRITE(0x400824, 0); NV_WRITE(0x400864, vramsz-1); NV_WRITE(0x400868, vramsz-1); /* interesting.. the below overwrites some of the tile setup above.. */ NV_WRITE(0x400B20, 0x00000000); NV_WRITE(0x400B04, 0xFFFFFFFF); NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMIN, 0); NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMIN, 0); NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff); NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff); return 0; }