void DMA_Stream::EnableTransferCompleteInterrupt(bool enable) { if (enable) { *_pDMA_SCR |= DMA_SCR_TCIE; } else { *_pDMA_SCR &= ~DMA_SCR_TCIE; } NVIC_SetEnable (_nvicIrqNumber); }
void ADC::_EnableInterrupt(uint16_t intMask, bool enable) { if (enable) { *_pADC_CR1 |= intMask; //enable interrupt on EOC NVIC_SetEnable(_irqNo); } else { *_pADC_CR1 &= ~intMask; //clear interrupt on EOC } }
void DMA_Stream::EnableHalfTransferInterrupt(bool enable) { if (enable) { *_pDMA_SCR |= DMA_SCR_HTIE; } else { *_pDMA_SCR &= ~DMA_SCR_HTIE; } NVIC_SetEnable (_nvicIrqNumber); }
void DMA_Stream::EnableDirectModeErrorInterrupt(bool enable) { if (enable) { *_pDMA_SCR |= DMA_SCR_DMEIE; } else { *_pDMA_SCR &= ~DMA_SCR_DMEIE; } NVIC_SetEnable (_nvicIrqNumber); }
void I2C::EnableEventInterrupt (bool enable) { if (enable) { *_pI2C_CR2 |= I2C_CR2_ITEVTEN; NVIC_SetEnable(_eventIrqNo); } else { *_pI2C_CR2 &= ~I2C_CR2_ITEVTEN; NVIC_ClearEnable(_eventIrqNo); } }
void SPI::_EnableInterrupt(uint16_t intMask, bool enable) { if (enable) { *_pSPI_CR2 |= intMask; NVIC_SetEnable(_irqNo); } else { *_pSPI_CR2 &= ~intMask; } }
void I2C::EnableErrorInterrupt (bool enable) { if (enable) { *_pI2C_CR2 |= I2C_CR2_ITERREN; NVIC_SetEnable(_errorIrqNo); } else { *_pI2C_CR2 &= ~I2C_CR2_ITERREN; NVIC_ClearEnable(_errorIrqNo); } }
void BKP::EnableTamperInterrupt(bool enable, BKP_TamperInterrupt_Handler* handler) { if (enable) { _intHandler = handler; BKP_CSR |= BKP_CSR_TPIE; NVIC_SetEnable(IRQn_TAMPER); } else { BKP_CSR &= ~BKP_CSR_TPIE; NVIC_ClearEnable(IRQn_TAMPER); } }
void EXTI::Enable(bool enable, volatile uint32_t* edgeReg, volatile uint32_t* eventOrIntReg) { if (enable) { if (_irqnNo != IRQn_NONE) { NVIC_SetEnable(_irqnNo); } *edgeReg |= (1 << _line); *eventOrIntReg |= (1 << _line); } else { if (_irqnNo != IRQn_NONE) { NVIC_ClearEnable(_irqnNo); } *edgeReg &= ~(1 << _line); *eventOrIntReg &= ~(1 << _line); } }