static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, const char *arch, ram_addr_t RAM_size, const char *boot_devices, uint32_t kernel_image, uint32_t kernel_size, const char *cmdline, uint32_t initrd_image, uint32_t initrd_size, uint32_t NVRAM_image, int width, int height, int depth, const uint8_t *macaddr) { unsigned int i; int sysp_end; uint8_t image[0x1ff0]; NvramClass *k = NVRAM_GET_CLASS(nvram); memset(image, '\0', sizeof(image)); /* OpenBIOS nvram variables partition */ sysp_end = chrp_nvram_create_system_partition(image, 0); /* Free space partition */ chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); for (i = 0; i < sizeof(image); i++) { (k->write)(nvram, i, image[i]); } return 0; }
static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, const char *arch, ram_addr_t RAM_size, const char *boot_devices, uint32_t kernel_image, uint32_t kernel_size, const char *cmdline, uint32_t initrd_image, uint32_t initrd_size, uint32_t NVRAM_image, int width, int height, int depth, const uint8_t *macaddr) { unsigned int i; uint32_t start, end; uint8_t image[0x1ff0]; struct OpenBIOS_nvpart_v1 *part_header; NvramClass *k = NVRAM_GET_CLASS(nvram); memset(image, '\0', sizeof(image)); start = 0; // OpenBIOS nvram variables // Variable partition part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; part_header->signature = OPENBIOS_PART_SYSTEM; pstrcpy(part_header->name, sizeof(part_header->name), "system"); end = start + sizeof(struct OpenBIOS_nvpart_v1); for (i = 0; i < nb_prom_envs; i++) end = OpenBIOS_set_var(image, end, prom_envs[i]); // End marker image[end++] = '\0'; end = start + ((end - start + 15) & ~15); OpenBIOS_finish_partition(part_header, end - start); // free partition start = end; part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; part_header->signature = OPENBIOS_PART_FREE; pstrcpy(part_header->name, sizeof(part_header->name), "free"); end = 0x1fd0; OpenBIOS_finish_partition(part_header, end - start); Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); for (i = 0; i < sizeof(image); i++) { (k->write)(nvram, i, image[i]); } return 0; }
static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) { sysctrl_t *sysctrl = opaque; trace_prep_io_800_writeb(addr - PPC_IO_BASE, val); switch (addr) { case 0x0092: /* Special port 92 */ /* Check soft reset asked */ if (val & 0x01) { qemu_irq_raise(sysctrl->reset_irq); } else { qemu_irq_lower(sysctrl->reset_irq); } /* Check LE mode */ if (val & 0x02) { sysctrl->endian = 1; } else { sysctrl->endian = 0; } break; case 0x0800: /* Motorola CPU configuration register : read-only */ break; case 0x0802: /* Motorola base module feature register : read-only */ break; case 0x0803: /* Motorola base module status register : read-only */ break; case 0x0808: /* Hardfile light register */ if (val & 1) sysctrl->state |= STATE_HARDFILE; else sysctrl->state &= ~STATE_HARDFILE; break; case 0x0810: /* Password protect 1 register */ if (sysctrl->nvram != NULL) { NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); (k->toggle_lock)(sysctrl->nvram, 1); } break; case 0x0812: /* Password protect 2 register */ if (sysctrl->nvram != NULL) { NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); (k->toggle_lock)(sysctrl->nvram, 2); } break; case 0x0814: /* L2 invalidate register */ // tlb_flush(first_cpu, 1); break; case 0x081C: /* system control register */ sysctrl->syscontrol = val & 0x0F; break; case 0x0850: /* I/O map type register */ sysctrl->contiguous_map = val & 0x01; qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map); break; default: printf("ERROR: unaffected IO port write: %04" PRIx32 " => %02" PRIx32"\n", addr, val); break; } }
static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val) { NvramClass *k = NVRAM_GET_CLASS(nvram); (k->write)(nvram, addr, val); }
/* NVRAM helpers */ static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr) { NvramClass *k = NVRAM_GET_CLASS(nvram); return (k->read)(nvram, addr); }