int disp_syncgen_setup(int module, struct disp_vsync_info *psync, struct disp_syncgen_param *par) { NX_DPC_DITHER RDither, GDither, BDither; CBOOL RGBMode = CFALSE; CBOOL EmbSync = (par->out_format == DPC_FORMAT_CCIR656 ? CTRUE : CFALSE); CBOOL ClkInv = par->clk_inv_lv0 | par->clk_inv_lv1; unsigned int delay_mask = par->delay_mask; int rgb_pvd = 0, hsync_cp1 = 7, vsync_fram = 7, de_cp2 = 7; int v_vso = 1, v_veo = 1, e_vso = 1, e_veo = 1; int interlace = 0; if (NULL == psync || NULL == par) { printk("Error, display.%d not set sync or pad clock inforamtion...\n", module); return -EINVAL; } interlace = psync->interlace; /* set delay mask */ if (delay_mask & DISP_SYNCGEN_DELAY_RGB_PVD) rgb_pvd = par->d_rgb_pvd; if (delay_mask & DISP_SYNCGEN_DELAY_HSYNC_CP1) hsync_cp1 = par->d_hsync_cp1; if (delay_mask & DISP_SYNCGEN_DELAY_VSYNC_FRAM) vsync_fram = par->d_vsync_fram; if (delay_mask & DISP_SYNCGEN_DELAY_DE_CP) de_cp2 = par->d_de_cp2; if (par->vs_start_offset != 0 || par->vs_end_offset != 0 || par->ev_start_offset != 0 || par->ev_end_offset != 0) { v_vso = par->vs_start_offset; v_veo = par->vs_end_offset; e_vso = par->ev_start_offset; e_veo = par->ev_end_offset; } if (((U32)NX_DPC_FORMAT_RGB555 == par->out_format) || ((U32)NX_DPC_FORMAT_MRGB555A == par->out_format) || ((U32)NX_DPC_FORMAT_MRGB555B == par->out_format)) { RDither = GDither = BDither = NX_DPC_DITHER_5BIT; RGBMode = CTRUE; } else if (((U32)NX_DPC_FORMAT_RGB565 == par->out_format) || ((U32)NX_DPC_FORMAT_MRGB565 == par->out_format)) { RDither = BDither = NX_DPC_DITHER_5BIT; GDither = NX_DPC_DITHER_6BIT, RGBMode = CTRUE; } else if (((U32)NX_DPC_FORMAT_RGB666 == par->out_format) || ((U32)NX_DPC_FORMAT_MRGB666 == par->out_format)) { RDither = GDither = BDither = NX_DPC_DITHER_6BIT; RGBMode = CTRUE; } else { RDither = GDither = BDither = NX_DPC_DITHER_BYPASS; RGBMode = CTRUE; } /* CLKGEN0/1 */ NX_DPC_SetClockSource (module, 0, psync->clk_src_lv0); NX_DPC_SetClockDivisor (module, 0, psync->clk_div_lv0); NX_DPC_SetClockSource (module, 1, psync->clk_src_lv1); NX_DPC_SetClockDivisor (module, 1, psync->clk_div_lv1); NX_DPC_SetClockOutDelay(module, 0, par->clk_delay_lv0); NX_DPC_SetClockOutDelay(module, 1, par->clk_delay_lv1); /* LCD out */ NX_DPC_SetMode(module, par->out_format, interlace, par->invert_field, RGBMode, par->swap_RB, par->yc_order, EmbSync, EmbSync, par->vclk_select, ClkInv, CFALSE); NX_DPC_SetHSync(module, psync->h_active_len, psync->h_sync_width, psync->h_front_porch, psync->h_back_porch, psync->h_sync_invert); NX_DPC_SetVSync(module, psync->v_active_len, psync->v_sync_width, psync->v_front_porch, psync->v_back_porch, psync->v_sync_invert, psync->v_active_len, psync->v_sync_width, psync->v_front_porch, psync->v_back_porch); NX_DPC_SetVSyncOffset(module, v_vso, v_veo, e_vso, e_veo); NX_DPC_SetDelay (module, rgb_pvd, hsync_cp1, vsync_fram, de_cp2); NX_DPC_SetDither(module, RDither, GDither, BDither); return 0; }
static CBOOL SetDisplayMode( NX_DISPLAY_MODE *pDisMode ) { U32 g_DPCIndex = 1; NX_DPC_PADCLK clock = NX_DPC_PADCLK_VCLK; NX_DISPLAY_TFTLCD *pTFTLCD = pDisMode->pTFTLCD; U32 dwVCLKDivider=0, dwSyncDelay=0; NX_DPC_DITHER RDither, GDither, BDither; CBOOL bEmbeddedSync, bRGBMode; RDither = GDither = BDither = NX_DPC_DITHER_5BIT; bEmbeddedSync = bRGBMode = CFALSE; /* if( g_DPCIndex ) { //NX_DPC_SetHorizontalUpScaler( g_DPCIndex, CTRUE, 320, 720 ); // DPC1's upscale test NX_DPC_SetHorizontalUpScaler( g_DPCIndex, CFALSE, 720, 720 ); } else NX_DPC_SetHorizontalUpScaler( g_DPCIndex, CFALSE, 2, 2 ); */ //-------------------------------------------------------------------------- NX_DPC_SetDPCEnable( g_DPCIndex, CFALSE ); NX_DPC_SetClockDivisorEnable(g_DPCIndex, CFALSE); //-------------------------------------------------------------------------- // RGB or YUV? NX_ASSERT( CNULL != pTFTLCD ); if( (U32)NX_DPC_FORMAT_MRGB888B >= pTFTLCD->dwOutputMode || (U32)NX_DPC_FORMAT_SRGB888 == pTFTLCD->dwOutputMode) { bRGBMode = CTRUE; } else { bRGBMode = CFALSE; } // VCLK = VCLK2 / ? if( ((U32)NX_DPC_FORMAT_RGB888 >= pTFTLCD->dwOutputMode) || ((U32)NX_DPC_FORMAT_CCIR601A == pTFTLCD->dwOutputMode) ) { dwVCLKDivider = 1; } else if((U32)NX_DPC_FORMAT_SRGB888 == pTFTLCD->dwOutputMode ) { dwVCLKDivider = 6; } else if((U32)NX_DPC_FORMAT_SRGBD8888 == pTFTLCD->dwOutputMode ) { dwVCLKDivider = 4; } else { dwVCLKDivider = 2; } // Dithering if( ((U32)NX_DPC_FORMAT_RGB555 == pTFTLCD->dwOutputMode) || ((U32)NX_DPC_FORMAT_MRGB555A == pTFTLCD->dwOutputMode) || ((U32)NX_DPC_FORMAT_MRGB555B == pTFTLCD->dwOutputMode) ) { RDither = GDither = BDither = NX_DPC_DITHER_5BIT; } else if( ((U32)NX_DPC_FORMAT_RGB565 == pTFTLCD->dwOutputMode) || ((U32)NX_DPC_FORMAT_MRGB565 == pTFTLCD->dwOutputMode) ) { RDither = BDither = NX_DPC_DITHER_5BIT; GDither = NX_DPC_DITHER_6BIT; } else if( ((U32)NX_DPC_FORMAT_RGB666 == pTFTLCD->dwOutputMode) || ((U32)NX_DPC_FORMAT_MRGB666 == pTFTLCD->dwOutputMode) ) { RDither = GDither = BDither = NX_DPC_DITHER_6BIT; } else { RDither = GDither = BDither = NX_DPC_DITHER_BYPASS; } // Embedded Sync? if( ((U32)NX_DPC_FORMAT_CCIR656 == pTFTLCD->dwOutputMode ) ) bEmbeddedSync = CTRUE; else bEmbeddedSync = CFALSE; /* if( bEmbeddedSync ) printk(KERN_INFO "[%s]DPC Format 656!!\n", __func__); */ // Sync Delay? if( bRGBMode ) { /* 2009/5/28 NXC-1000 databook 26.4.6 Delay if( 0 == g_DPCIndex ) dwSyncDelay = 7 * dwVCLKDivider; // Primary DPC else dwSyncDelay = 4 * dwVCLKDivider; // Secondary DPC */ dwSyncDelay = 7 * dwVCLKDivider; } else { dwSyncDelay = 6 * dwVCLKDivider; } //-------------------------------------------------------------------------- // VCLK2 : CLKGEN0 NX_DPC_SetClockSource (g_DPCIndex, 0, pTFTLCD->dwClockSource); // CLKSRCSEL NX_DPC_SetClockDivisor (g_DPCIndex, 0, pTFTLCD->dwClockDivider); // CLKDIV NX_DPC_SetClockOutDelay(g_DPCIndex, 0, pTFTLCD->dwClockDelay); // OUTCLKDELAY // VCLK : CLKGEN1 NX_DPC_SetClockSource (g_DPCIndex, 1, 7); // CLKSRCSEL : CLKGEN0's out NX_DPC_SetClockDivisor (g_DPCIndex, 1, dwVCLKDivider); // CLKDIV NX_DPC_SetClockOutDelay(g_DPCIndex, 1, pTFTLCD->dwClockDelay); // OUTCLKDELAY //-------------------------------------------------------------------------- clock = (pTFTLCD->bDualEdge) ? NX_DPC_PADCLK_VCLK : NX_DPC_PADCLK_VCLK2; if(pTFTLCD->dwOutputMode == NX_DPC_FORMAT_SRGBD8888) clock = NX_DPC_PADCLK_VCLK; else if(pTFTLCD->dwOutputMode == NX_DPC_FORMAT_SRGB888) clock = NX_DPC_PADCLK_VCLK3; NX_DPC_SetMode(g_DPCIndex, (NX_DPC_FORMAT)pTFTLCD->dwOutputMode, // FORMAT pTFTLCD->bInterlace, // SCANMODE pTFTLCD->bInvertField, // POLFIELD bRGBMode, // RGBMODE CFALSE, // SWAPRB NX_DPC_YCORDER_CbYCrY , // YCORDER (bEmbeddedSync) ? CTRUE : CFALSE, // YCCLIP bEmbeddedSync, // Embedded sync clock, // PADCLKSEL pTFTLCD->bClockRisingEdge, // PADCLKINV pTFTLCD->bDualView ); NX_DPC_SetHSync( g_DPCIndex, pTFTLCD->dwHorActive, pTFTLCD->dwHorSyncWidth, pTFTLCD->dwHorFrontPorch, pTFTLCD->dwHorBackPorch, pTFTLCD->bHorSyncHighActive ); NX_DPC_SetVSync( g_DPCIndex, pTFTLCD->dwVerActive, pTFTLCD->dwVerSyncWidth, pTFTLCD->dwVerFrontPorch, pTFTLCD->dwVerBackPorch, pTFTLCD->bVerSyncHighActive, pTFTLCD->dwEvenVerActive, pTFTLCD->dwEvenVerSyncWidth, pTFTLCD->dwEvenVerFrontPorch, pTFTLCD->dwEvenVerBackPorch ); NX_DPC_SetVSyncOffset( g_DPCIndex, pTFTLCD->dwVerSyncStartOffset, pTFTLCD->dwVerSyncEndOffset, pTFTLCD->dwEvenVerSyncStartOffset, pTFTLCD->dwEvenVerSyncEndOffset ); NX_DPC_SetDelay(g_DPCIndex, 0, // DELAYRGB dwSyncDelay, // DELAYHS_CP1 dwSyncDelay, // DELAYVS_FRAM dwSyncDelay ); // DELAYDE_CP2 if( bRGBMode ) { NX_DPC_SetDither( g_DPCIndex, RDither, GDither, BDither ); } else { NX_DPC_SetDither( g_DPCIndex, NX_DPC_DITHER_BYPASS, NX_DPC_DITHER_BYPASS, NX_DPC_DITHER_BYPASS ); } //-------------------------------------------------------------------------- /* if( 1 == g_DPCIndex ) { if( CNULL != pEncoderMode ) { NX_DPC_SetENCEnable( g_DPCIndex, CTRUE ); //NX_TIMER_TickCountDelay( 100 ); //NX_DPC_SetClockDivisorEnable( g_DPCIndex, CTRUE ); //NX_TIMER_TickCountDelay( 100 ); //NX_DPC_SetENCEnable( g_DPCIndex, CFALSE ); //NX_TIMER_TickCountDelay( 100 ); //NX_DPC_SetClockDivisorEnable( g_DPCIndex, CFALSE ); //NX_TIMER_TickCountDelay( 100 ); NX_DPC_SetClockDivisorEnable(g_DPCIndex, CTRUE); // CLKENB : Provides internal operating clock. NX_DPC_SetENCEnable( g_DPCIndex, CTRUE ); //NX_DPC_SetVideoEncoderPowerDown( g_DPCIndex, CTRUE ); NX_DPC_SetVideoEncoderMode( g_DPCIndex, (NX_DPC_VBS)pEncoderMode->dwBroadcast, pEncoderMode->bPedestal ) ; NX_DPC_SetVideoEncoderFSCAdjust( g_DPCIndex, 0 ); NX_DPC_SetVideoEncoderBandwidth( g_DPCIndex, (NX_DPC_BANDWIDTH)pEncoderMode->dwYBandWidth, (NX_DPC_BANDWIDTH)pEncoderMode->dwCBandWidth ) ; NX_DPC_SetVideoEncoderColorControl( g_DPCIndex, 0, 0, 0, 0, 0 ); NX_DPC_SetVideoEncoderTiming( g_DPCIndex, pEncoderMode->dwHorSyncStart, pEncoderMode->dwHorSyncEnd, pEncoderMode->dwVerSyncStart, pEncoderMode->dwVerSyncEnd ); NX_DPC_SetVideoEncoderPowerDown( g_DPCIndex, CFALSE ); NX_DPC_SetENCEnable( g_DPCIndex, CTRUE ); } else { NX_DPC_SetENCEnable( g_DPCIndex, CFALSE ); } } */ //-------------------------------------------------------------------------- NX_DPC_SetClockDivisorEnable(g_DPCIndex, CTRUE); // CLKENB : Provides internal operating clock. NX_DISPLAYTOP_SetPrimaryMUX(2 * g_DPCIndex); NX_DISPLAYTOP_SetPADClock(PADMUX_SecondaryMLC, PADCLK_InvCLK ); // NX_DPC_SetDPCEnable( g_DPCIndex, CTRUE ); NX_DPC_SetEnable( g_DPCIndex, CTRUE, CFALSE, CFALSE, CFALSE, CTRUE ); return CTRUE; }