C++ (Cpp) NX_TIEOFF_Set示例

示例#1

0

显示文件

文件： display_mipi.c 项目： advx9600/kernel-4.4-RuiEr

static void mipi_initialize(void)
{
	int clkid = DISP_CLOCK_MIPI;
	int index = 0;

	NX_TIEOFF_Set(TIEOFFINDEX_OF_MIPI0_NX_DPSRAM_1R1W_EMAA, 3);
	NX_TIEOFF_Set(TIEOFFINDEX_OF_MIPI0_NX_DPSRAM_1R1W_EMAB, 3);

	if (! nxp_soc_peri_reset_status(NX_MIPI_GetResetNumber(index, NX_MIPI_RST))) {
	    nxp_soc_peri_reset_enter(NX_MIPI_GetResetNumber(index, NX_MIPI_RST));
    	nxp_soc_peri_reset_enter(NX_MIPI_GetResetNumber(index, NX_MIPI_RST_DSI_I));
    	nxp_soc_peri_reset_enter(NX_MIPI_GetResetNumber(index, NX_MIPI_RST_PHY_S));
    	nxp_soc_peri_reset_enter(NX_MIPI_GetResetNumber(index, NX_MIPI_RST_PHY_M));
    	nxp_soc_peri_reset_exit (NX_MIPI_GetResetNumber(index, NX_MIPI_RST));
    	nxp_soc_peri_reset_exit (NX_MIPI_GetResetNumber(index, NX_MIPI_RST_DSI_I));
		nxp_soc_peri_reset_exit (NX_MIPI_GetResetNumber(index, NX_MIPI_RST_PHY_S));
    	nxp_soc_peri_reset_exit (NX_MIPI_GetResetNumber(index, NX_MIPI_RST_PHY_M));
    }

	/* BASE : CLKGEN, MIPI */
	NX_DISPTOP_CLKGEN_SetBaseAddress(clkid, (U32)IO_ADDRESS(NX_DISPTOP_CLKGEN_GetPhysicalAddress(clkid)));
	NX_DISPTOP_CLKGEN_SetClockPClkMode(clkid, NX_PCLKMODE_ALWAYS);

	/* BASE : MIPI */
	NX_MIPI_Initialize();
    NX_MIPI_SetBaseAddress(0, IO_ADDRESS(NX_MIPI_GetPhysicalAddress(0)));
	NX_MIPI_OpenModule(0);
}

示例#2

0

显示文件

文件： display_mipi.c 项目： advx9600/kernel-4.4-RuiEr

static void mipi_resume(struct disp_process_dev *pdev)
{
	int index = 0;
	PM_DBGOUT("%s\n", __func__);

	NX_TIEOFF_Set(TIEOFFINDEX_OF_MIPI0_NX_DPSRAM_1R1W_EMAA, 3);
	NX_TIEOFF_Set(TIEOFFINDEX_OF_MIPI0_NX_DPSRAM_1R1W_EMAB, 3);
	if (! nxp_soc_peri_reset_status(NX_MIPI_GetResetNumber(index, NX_MIPI_RST))) {
	    nxp_soc_peri_reset_enter(NX_MIPI_GetResetNumber(index, NX_MIPI_RST));
    	nxp_soc_peri_reset_enter(NX_MIPI_GetResetNumber(index, NX_MIPI_RST_DSI_I));
    	nxp_soc_peri_reset_enter(NX_MIPI_GetResetNumber(index, NX_MIPI_RST_PHY_S));
    	nxp_soc_peri_reset_enter(NX_MIPI_GetResetNumber(index, NX_MIPI_RST_PHY_M));
    	nxp_soc_peri_reset_exit (NX_MIPI_GetResetNumber(index, NX_MIPI_RST));
    	nxp_soc_peri_reset_exit (NX_MIPI_GetResetNumber(index, NX_MIPI_RST_DSI_I));
		nxp_soc_peri_reset_exit (NX_MIPI_GetResetNumber(index, NX_MIPI_RST_PHY_S));
    	nxp_soc_peri_reset_exit (NX_MIPI_GetResetNumber(index, NX_MIPI_RST_PHY_M));
    }
	mipi_enable(pdev, 1);
}

示例#3

0

显示文件

文件： lldebug.c 项目： newwind3/study

inline static void uart_init(void)
{
	U32 CLKENB = UART_CLKG_BASE;
	U32 CLKGEN = UART_CLKG_BASE + 0x04;
	struct uart_data *pdat = &udata;
	struct s5p_uart *uart = (struct s5p_uart *)UART_PHYS_BASE;
	unsigned int baudrate = UART_DEBUG_BAUDRATE;
	unsigned int clkval;

	/* Clock Generotor & reset */
	if (0 == pdat->rate) {
		u32 val = UART_DEBUG_HZ / baudrate;
		pdat->rate = calc_uart_clock(UART_DEBUG_HZ, &pdat->pll, &pdat->div);
		pdat->ubrdiv = (val/16) - 1;
		pdat->udivslot = udivslot[val % 16];
		/* NORMAL | No parity | 1 stop | 8bit */
		pdat->ulcon = (((0 & 0x1)<<6) | ((0 & 0x3)<<3) | ((0 & 0x1)<<2) | ((3 & 0x3)<<0));
		/* Tx FIFO clr | Rx FIFO clr | FIFOs EN */
		pdat->ufcon = (((1 & 0x1)<<1) | ((1 & 0x1)<<0));
	}

	/* check reset */
	if (!nxp_soc_peri_reset_status(RESET_UART_ID)) {
		NX_TIEOFF_Set(TIEOFF_USESMC  , 0);
		NX_TIEOFF_Set(TIEOFF_SMCTXENB, 0);
		NX_TIEOFF_Set(TIEOFF_SMCRXENB, 0);
		nxp_soc_peri_reset_set(RESET_UART_ID);
	}

	/* check pll : alaway enable clkgen */
	clkval = readl(CLKGEN) & ~(0x07<<2) & ~(0xFF<<5);
	writel((clkval|(pdat->pll<<2)|((pdat->div-1)<<5)), CLKGEN);
	writel((readl(CLKENB)|(1<<2)), CLKENB);

	/* Uart Register */
	writel(pdat->ufcon, &uart->ufcon);
	writel(pdat->ulcon, &uart->ulcon);
	writel(pdat->ubrdiv, &uart->ubrdiv);
	writew(pdat->udivslot, &uart->rest.slot);
}

示例#4

0

显示文件

文件： board.c 项目： projectnano/zeus

int board_late_init(void)
{
#if defined(CONFIG_SYS_MMC_BOOT_DEV)
	char boot[16];
	sprintf(boot, "mmc dev %d", CONFIG_SYS_MMC_BOOT_DEV);
	run_command(boot, 0);
#endif

#if defined CONFIG_RECOVERY_BOOT
    if (RECOVERY_SIGNATURE == readl(SCR_RESET_SIG_READ)) {
        writel((-1UL), SCR_RESET_SIG_RESET); /* clear */

        printf("RECOVERY BOOT\n");
        bd_display_run(CONFIG_CMD_LOGO_WALLPAPERS, CFG_LCD_PRI_PWM_DUTYCYCLE, 1);
        run_command(CONFIG_CMD_RECOVERY_BOOT, 0);	/* recovery boot */
    }
    writel((-1UL), SCR_RESET_SIG_RESET);
#endif /* CONFIG_RECOVERY_BOOT */

#if defined(CONFIG_BAT_CHECK)
	{
		int ret =0;
		int bat_check_skip = 0;
	    // psw0523 for cts
	    // bat_check_skip = 1;

#if defined(CONFIG_DISPLAY_OUT)
		ret = power_battery_check(bat_check_skip, bd_display_run);
#else
		ret = power_battery_check(bat_check_skip, NULL);
#endif

		if(ret == 1)
			auto_update(UPDATE_KEY, UPDATE_CHECK_TIME);
	}
#else /* CONFIG_BAT_CHECK */

	// mipi reset
    NX_TIEOFF_Set(TIEOFFINDEX_OF_MIPI0_NX_DPSRAM_1R1W_EMAA, 3);
    NX_TIEOFF_Set(TIEOFFINDEX_OF_MIPI0_NX_DPSRAM_1R1W_EMAB, 3);

	NX_RSTCON_SetnRST(RESET_ID_MIPI, RSTCON_nDISABLE);
	NX_RSTCON_SetnRST(RESET_ID_MIPI_DSI, RSTCON_nDISABLE);
	NX_RSTCON_SetnRST(RESET_ID_MIPI_CSI, RSTCON_nDISABLE);
	NX_RSTCON_SetnRST(RESET_ID_MIPI_PHY_S, RSTCON_nDISABLE);
	NX_RSTCON_SetnRST(RESET_ID_MIPI_PHY_M, RSTCON_nDISABLE);
	NX_RSTCON_SetnRST(RESET_ID_MIPI, RSTCON_nENABLE);
	NX_RSTCON_SetnRST(RESET_ID_MIPI_DSI, RSTCON_nENABLE);
	NX_RSTCON_SetnRST(RESET_ID_MIPI_PHY_S, RSTCON_nENABLE);
	NX_RSTCON_SetnRST(RESET_ID_MIPI_PHY_M, RSTCON_nENABLE);
	// ac97 reset
	NX_RSTCON_SetnRST(RESET_ID_AC97, RSTCON_nDISABLE);
	NX_RSTCON_SetnRST(RESET_ID_AC97, RSTCON_nENABLE);
	// scaler reset
	NX_RSTCON_SetnRST(RESET_ID_SCALER, RSTCON_nDISABLE);
	NX_RSTCON_SetnRST(RESET_ID_SCALER, RSTCON_nENABLE);
	// pdm reset
	NX_CLKGEN_SetClockPClkMode(CLOCKINDEX_OF_PDM_MODULE, NX_PCLKMODE_ALWAYS); // PCLK Always
	NX_RSTCON_SetnRST(RESET_ID_PDM, RSTCON_nDISABLE);
	NX_RSTCON_SetnRST(RESET_ID_PDM, RSTCON_nENABLE);
	// mpegtsi reset
	NX_RSTCON_SetnRST(RESET_ID_MPEGTSI, RSTCON_nDISABLE);
	NX_RSTCON_SetnRST(RESET_ID_MPEGTSI, RSTCON_nENABLE);
	// crypto reset
	NX_CLKGEN_SetClockPClkMode(CLOCKINDEX_OF_CRYPTO_MODULE, NX_PCLKMODE_ALWAYS); // PCLK Always
	NX_RSTCON_SetnRST(RESET_ID_CRYPTO, RSTCON_nDISABLE);
	NX_RSTCON_SetnRST(RESET_ID_CRYPTO, RSTCON_nENABLE);
	// spi1 reset
	NX_RSTCON_SetnRST(RESET_ID_SSP1_P, RSTCON_nDISABLE);
	NX_RSTCON_SetnRST(RESET_ID_SSP1, RSTCON_nDISABLE);
	NX_RSTCON_SetnRST(RESET_ID_SSP1_P, RSTCON_nENABLE);
	NX_RSTCON_SetnRST(RESET_ID_SSP1, RSTCON_nENABLE);
	// spi2 reset
	NX_RSTCON_SetnRST(RESET_ID_SSP2_P, RSTCON_nDISABLE);
	NX_RSTCON_SetnRST(RESET_ID_SSP2, RSTCON_nDISABLE);
	NX_RSTCON_SetnRST(RESET_ID_SSP2_P, RSTCON_nENABLE);
	NX_RSTCON_SetnRST(RESET_ID_SSP2, RSTCON_nENABLE);

	// vip 0/1 reset
	NX_CLKGEN_SetClockBClkMode(CLOCKINDEX_OF_VIP0_MODULE, NX_BCLKMODE_DYNAMIC);
    NX_CLKGEN_SetClockDivisorEnable(CLOCKINDEX_OF_VIP0_MODULE, CTRUE);
   	NX_RSTCON_SetnRST(RESET_ID_VIP0, RSTCON_nDISABLE);
	NX_RSTCON_SetnRST(RESET_ID_VIP0, RSTCON_nENABLE);
	NX_CLKGEN_SetClockBClkMode(CLOCKINDEX_OF_VIP1_MODULE, NX_BCLKMODE_DYNAMIC);
	NX_CLKGEN_SetClockDivisorEnable(CLOCKINDEX_OF_VIP1_MODULE, CTRUE);
	NX_RSTCON_SetnRST(RESET_ID_VIP1, RSTCON_nDISABLE);
	NX_RSTCON_SetnRST(RESET_ID_VIP1, RSTCON_nENABLE);

#if defined(CONFIG_DISPLAY_OUT)
	bd_display_run(CONFIG_CMD_LOGO_WALLPAPERS, CFG_LCD_PRI_PWM_DUTYCYCLE, 1);
#endif

#ifdef CONFIG_CMD_NET
	bd_eth_init();
#endif

	/* Temp check gpio to update */
	auto_update(UPDATE_KEY, UPDATE_CHECK_TIME);

#endif /* CONFIG_BAT_CHECK */

	return 0;
}

示例#5

0

显示文件

文件： s5p4418.c 项目： iTOP4418/kernel-3.4.39

void nxp_cpu_core_shutdown(int core)
{
	printk(KERN_INFO "cpu.%d shutdown ...\n", core);
	NX_TIEOFF_Set(core_power[core][0], 1);
	NX_TIEOFF_Set(core_power[core][1], 1);
}

示例#6

0

显示文件

文件： loopback-sensor.c 项目： iTOP4418/kernel-3.4.39

static void _set_hdmi_clk_27MHz(void)
{
    NX_HDMI_SetBaseAddress(0, (void *)IO_ADDRESS(NX_HDMI_GetPhysicalAddress(0)));

    NX_TIEOFF_Initialize();
    NX_TIEOFF_SetBaseAddress((void *)IO_ADDRESS(NX_TIEOFF_GetPhysicalAddress()));
    NX_TIEOFF_Set(TIEOFFINDEX_OF_DISPLAYTOP0_i_HDMI_PHY_REFCLK_SEL, 1);

    // HDMI PCLK Enable
    NX_DISPTOP_CLKGEN_SetBaseAddress(HDMI_CLKGEN, (void *)IO_ADDRESS(NX_DISPTOP_CLKGEN_GetPhysicalAddress(HDMI_CLKGEN)));
    NX_DISPTOP_CLKGEN_SetClockPClkMode(HDMI_CLKGEN, NX_PCLKMODE_ALWAYS);

    // Enter Reset
    NX_RSTCON_SetRST  (NX_HDMI_GetResetNumber(0, i_nRST_PHY) , 0);
    NX_RSTCON_SetRST  (NX_HDMI_GetResetNumber(0, i_nRST)     , 0); // APB

    // Release Reset
    NX_RSTCON_SetRST  (NX_HDMI_GetResetNumber(0, i_nRST_PHY) , 1);
    NX_RSTCON_SetRST  (NX_HDMI_GetResetNumber(0, i_nRST)     , 1); // APB

    NX_DISPTOP_CLKGEN_SetClockPClkMode      (HDMI_CLKGEN, NX_PCLKMODE_ALWAYS);

    NX_HDMI_SetReg( 0, HDMI_PHY_Reg7C, (0<<7) ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg7C, (0<<7) );    /// MODE_SET_DONE : APB Set
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg04, (0<<4) ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg04, (0<<4) );    ///CLK_SEL : REF OSC or INT_CLK
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg24, (1<<7) ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg24, (1<<7) );    // INT REFCLK : ³»ºÎÀÇ syscon¿¡¼ ¹Þ´Â clock
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg04, 0xD1   ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg04, 0xD1   );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg08, 0x22   ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg08, 0x22   );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg0C, 0x51   ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg0C, 0x51   );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg10, 0x40   ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg10, 0x40   );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg14, 0x8    ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg14, 0x8    );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg18, 0xFC   ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg18, 0xFC   );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg1C, 0xE0   ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg1C, 0xE0   );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg20, 0x98   ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg20, 0x98   );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg24, 0xE8   ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg24, 0xE8   );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg28, 0xCB   ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg28, 0xCB   );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg2C, 0xD8   ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg2C, 0xD8   );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg30, 0x45   ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg30, 0x45   );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg34, 0xA0   ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg34, 0xA0   );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg38, 0xAC   ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg38, 0xAC   );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg3C, 0x80   ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg3C, 0x80   );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg40, 0x6    ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg40, 0x6    );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg44, 0x80   ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg44, 0x80   );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg48, 0x9    ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg48, 0x9    );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg4C, 0x84   ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg4C, 0x84   );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg50, 0x5    ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg50, 0x5    );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg54, 0x22   ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg54, 0x22   );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg58, 0x24   ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg58, 0x24   );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg5C, 0x86   ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg5C, 0x86   );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg60, 0x54   ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg60, 0x54   );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg64, 0xE4   ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg64, 0xE4   );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg68, 0x24   ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg68, 0x24   );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg6C, 0x0    ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg6C, 0x0    );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg70, 0x0    ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg70, 0x0    );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg74, 0x0    ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg74, 0x0    );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg78, 0x1    ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg78, 0x1    );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg7C, 0x80   ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg7C, 0x80   );
    NX_HDMI_SetReg( 0, HDMI_PHY_Reg7C, (1<<7) ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg7C, (1<<7) );    /// MODE_SET_DONE : APB Set Done

    // wait phy ready
    {
        U32 Is_HDMI_PHY_READY = CFALSE;
        while(Is_HDMI_PHY_READY == CFALSE) {
            if(NX_HDMI_GetReg( 0, HDMI_LINK_PHY_STATUS_0 ) & 0x01) {
                Is_HDMI_PHY_READY = CTRUE;
            }
        }
    }
}