/* * Read QLM and return mode. */ enum cvmx_qlm_mode cvmx_qlm_get_mode(int qlm) { if (OCTEON_IS_OCTEON2()) return __cvmx_qlm_get_mode_cn6xxx(qlm); else if (OCTEON_IS_MODEL(OCTEON_CN70XX)) return __cvmx_qlm_get_mode_cn70xx(qlm); else if (OCTEON_IS_MODEL(OCTEON_CN78XX)) return __cvmx_qlm_get_mode_cn78xx(qlm); return CVMX_QLM_MODE_DISABLED; }
void __init plat_swiotlb_setup(void) { int i; phys_addr_t max_addr; phys_addr_t addr_size; size_t swiotlbsize; unsigned long swiotlb_nslabs; max_addr = 0; addr_size = 0; for (i = 0 ; i < boot_mem_map.nr_map; i++) { struct boot_mem_map_entry *e = &boot_mem_map.map[i]; if (e->type != BOOT_MEM_RAM && e->type != BOOT_MEM_INIT_RAM) continue; /* These addresses map low for PCI. */ if (e->addr > 0x410000000ull && !OCTEON_IS_OCTEON2()) continue; addr_size += e->size; if (max_addr < e->addr + e->size) max_addr = e->addr + e->size; } swiotlbsize = PAGE_SIZE; #ifdef CONFIG_PCI /* * For OCTEON_DMA_BAR_TYPE_SMALL, size the iotlb at 1/4 memory * size to a maximum of 64MB */ if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) { swiotlbsize = addr_size / 4; if (swiotlbsize > 64 * (1<<20)) swiotlbsize = 64 * (1<<20); } else if (max_addr > 0xf0000000ul) { /* * Otherwise only allocate a big iotlb if there is * memory past the BAR1 hole. */ swiotlbsize = 64 * (1<<20); } #endif #ifdef CONFIG_USB_OHCI_HCD_PLATFORM /* OCTEON II ohci is only 32-bit. */ if (OCTEON_IS_OCTEON2() && max_addr >= 0x100000000ul) swiotlbsize = 64 * (1<<20); #endif swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT; swiotlb_nslabs = ALIGN(swiotlb_nslabs, IO_TLB_SEGSIZE); swiotlbsize = swiotlb_nslabs << IO_TLB_SHIFT; octeon_swiotlb = memblock_alloc_low(swiotlbsize, PAGE_SIZE); if (!octeon_swiotlb) panic("%s: Failed to allocate %zu bytes align=%lx\n", __func__, swiotlbsize, PAGE_SIZE); if (swiotlb_init_with_tbl(octeon_swiotlb, swiotlb_nslabs, 1) == -ENOMEM) panic("Cannot allocate SWIOTLB buffer"); }
/** * Get the speed (Gbaud) of the QLM in Mhz. * * @param qlm QLM to examine * * @return Speed in Mhz */ int cvmx_qlm_get_gbaud_mhz(int qlm) { if (OCTEON_IS_MODEL(OCTEON_CN63XX)) { if (qlm == 2) { cvmx_gmxx_inf_mode_t inf_mode; inf_mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(0)); switch (inf_mode.s.speed) { case 0: return 5000; /* 5 Gbaud */ case 1: return 2500; /* 2.5 Gbaud */ case 2: return 2500; /* 2.5 Gbaud */ case 3: return 1250; /* 1.25 Gbaud */ case 4: return 1250; /* 1.25 Gbaud */ case 5: return 6250; /* 6.25 Gbaud */ case 6: return 5000; /* 5 Gbaud */ case 7: return 2500; /* 2.5 Gbaud */ case 8: return 3125; /* 3.125 Gbaud */ case 9: return 2500; /* 2.5 Gbaud */ case 10: return 1250; /* 1.25 Gbaud */ case 11: return 5000; /* 5 Gbaud */ case 12: return 6250; /* 6.25 Gbaud */ case 13: return 3750; /* 3.75 Gbaud */ case 14: return 3125; /* 3.125 Gbaud */ default: return 0; /* Disabled */ } } else { cvmx_sriox_status_reg_t status_reg; status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(qlm)); if (status_reg.s.srio) { cvmx_sriomaintx_port_0_ctl2_t sriomaintx_port_0_ctl2; sriomaintx_port_0_ctl2.u32 = cvmx_read_csr(CVMX_SRIOMAINTX_PORT_0_CTL2(qlm)); switch (sriomaintx_port_0_ctl2.s.sel_baud) { case 1: return 1250; /* 1.25 Gbaud */ case 2: return 2500; /* 2.5 Gbaud */ case 3: return 3125; /* 3.125 Gbaud */ case 4: return 5000; /* 5 Gbaud */ case 5: return 6250; /* 6.250 Gbaud */ default: return 0; /* Disabled */ } } else { cvmx_pciercx_cfg032_t pciercx_cfg032; pciercx_cfg032.u32 = cvmx_read_csr(CVMX_PCIERCX_CFG032(qlm)); switch (pciercx_cfg032.s.ls) { case 1: return 2500; case 2: return 5000; case 4: return 8000; default: { cvmx_mio_rst_boot_t mio_rst_boot; mio_rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT); if ((qlm == 0) && mio_rst_boot.s.qlm0_spd == 0xf) return 0; if ((qlm == 1) && mio_rst_boot.s.qlm1_spd == 0xf) return 0; return 5000; /* Best guess I can make */ } } } } } else if (OCTEON_IS_OCTEON2()) { cvmx_mio_qlmx_cfg_t qlm_cfg; qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(qlm)); switch (qlm_cfg.s.qlm_spd) { case 0: return 5000; /* 5 Gbaud */ case 1: return 2500; /* 2.5 Gbaud */ case 2: return 2500; /* 2.5 Gbaud */ case 3: return 1250; /* 1.25 Gbaud */ case 4: return 1250; /* 1.25 Gbaud */ case 5: return 6250; /* 6.25 Gbaud */ case 6: return 5000; /* 5 Gbaud */ case 7: return 2500; /* 2.5 Gbaud */ case 8: return 3125; /* 3.125 Gbaud */ case 9: return 2500; /* 2.5 Gbaud */ case 10: return 1250; /* 1.25 Gbaud */ case 11: return 5000; /* 5 Gbaud */ case 12: return 6250; /* 6.25 Gbaud */ case 13: return 3750; /* 3.75 Gbaud */ case 14: return 3125; /* 3.125 Gbaud */ default: return 0; /* Disabled */ } } else if (OCTEON_IS_MODEL(OCTEON_CN70XX)) { cvmx_gserx_dlmx_mpll_multiplier_t mpll_multiplier; uint64_t meas_refclock; uint64_t freq; /* Measure the reference clock */ meas_refclock = cvmx_qlm_measure_clock(qlm); /* Multiply to get the final frequency */ mpll_multiplier.u64 = cvmx_read_csr(CVMX_GSERX_DLMX_MPLL_MULTIPLIER(qlm, 0)); freq = meas_refclock * mpll_multiplier.s.mpll_multiplier; freq = (freq + 500000) / 1000000; return freq; } return 0; }
/* Version of octeon_model_get_string() that takes buffer as argument, as ** running early in u-boot static/global variables don't work when running from ** flash */ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer) { const char *family; const char *core_model; char pass[4]; #ifndef CVMX_BUILD_FOR_UBOOT int clock_mhz; #endif const char *suffix; cvmx_l2d_fus3_t fus3; int num_cores; cvmx_mio_fus_dat2_t fus_dat2; cvmx_mio_fus_dat3_t fus_dat3; char fuse_model[10]; char fuse_suffix[4] = {0}; uint64_t fuse_data = 0; fus3.u64 = 0; if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)) fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3); fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2); fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3); if (OCTEON_IS_MODEL(OCTEON_CN78XX)) num_cores = cvmx_pop(cvmx_read_csr(CVMX_CIU3_FUSE)); else num_cores = cvmx_pop(cvmx_read_csr(CVMX_CIU_FUSE)); /* Make sure the non existent devices look disabled */ switch ((chip_id >> 8) & 0xff) { case 6: /* CN50XX */ case 2: /* CN30XX */ fus_dat3.s.nodfa_dte = 1; fus_dat3.s.nozip = 1; break; case 4: /* CN57XX or CN56XX */ fus_dat3.s.nodfa_dte = 1; break; default: break; } /* Make a guess at the suffix */ /* NSP = everything */ /* EXP = No crypto */ /* SCP = No DFA, No zip */ /* CP = No DFA, No crypto, No zip */ if (fus_dat3.s.nodfa_dte) { if (fus_dat2.s.nocrypto) suffix = "CP"; else suffix = "SCP"; } else if (fus_dat2.s.nocrypto) suffix = "EXP"; else suffix = "NSP"; /* Assume pass number is encoded using <5:3><2:0>. Exceptions will be fixed later */ sprintf(pass, "%d.%d", (int)((chip_id >> 3) & 7) + 1, (int)chip_id & 7); /* Use the number of cores to determine the last 2 digits of the model number. There are some exceptions that are fixed later */ switch (num_cores) { case 32: core_model = "80"; break; case 24: core_model = "70"; break; case 16: core_model = "60"; break; case 15: core_model = "58"; break; case 14: core_model = "55"; break; case 13: core_model = "52"; break; case 12: core_model = "50"; break; case 11: core_model = "48"; break; case 10: core_model = "45"; break; case 9: core_model = "42"; break; case 8: core_model = "40"; break; case 7: core_model = "38"; break; case 6: core_model = "34"; break; case 5: core_model = "32"; break; case 4: core_model = "30"; break; case 3: core_model = "25"; break; case 2: core_model = "20"; break; case 1: core_model = "10"; break; default: core_model = "XX"; break; } /* Now figure out the family, the first two digits */ switch ((chip_id >> 8) & 0xff) { case 0: /* CN38XX, CN37XX or CN36XX */ if (fus3.cn38xx.crip_512k) { /* For some unknown reason, the 16 core one is called 37 instead of 36 */ if (num_cores >= 16) family = "37"; else family = "36"; } else family = "38"; /* This series of chips didn't follow the standard pass numbering */ switch (chip_id & 0xf) { case 0: strcpy(pass, "1.X"); break; case 1: strcpy(pass, "2.X"); break; case 3: strcpy(pass, "3.X"); break; default: strcpy(pass, "X.X"); break; } break; case 1: /* CN31XX or CN3020 */ if ((chip_id & 0x10) || fus3.cn31xx.crip_128k) family = "30"; else family = "31"; /* This series of chips didn't follow the standard pass numbering */ switch (chip_id & 0xf) { case 0: strcpy(pass, "1.0"); break; case 2: strcpy(pass, "1.1"); break; default: strcpy(pass, "X.X"); break; } break; case 2: /* CN3010 or CN3005 */ family = "30"; /* A chip with half cache is an 05 */ if (fus3.cn30xx.crip_64k) core_model = "05"; /* This series of chips didn't follow the standard pass numbering */ switch (chip_id & 0xf) { case 0: strcpy(pass, "1.0"); break; case 2: strcpy(pass, "1.1"); break; default: strcpy(pass, "X.X"); break; } break; case 3: /* CN58XX */ family = "58"; /* Special case. 4 core, half cache (CP with half cache) */ if ((num_cores == 4) && fus3.cn58xx.crip_1024k && !strncmp(suffix, "CP", 2)) core_model = "29"; /* Pass 1 uses different encodings for pass numbers */ if ((chip_id & 0xFF) < 0x8) { switch (chip_id & 0x3) { case 0: strcpy(pass, "1.0"); break; case 1: strcpy(pass, "1.1"); break; case 3: strcpy(pass, "1.2"); break; default: strcpy(pass, "1.X"); break; } } break; case 4: /* CN57XX, CN56XX, CN55XX, CN54XX */ if (fus_dat2.cn56xx.raid_en) { if (fus3.cn56xx.crip_1024k) family = "55"; else family = "57"; if (fus_dat2.cn56xx.nocrypto) suffix = "SP"; else suffix = "SSP"; } else { if (fus_dat2.cn56xx.nocrypto) suffix = "CP"; else { suffix = "NSP"; if (fus_dat3.s.nozip) suffix = "SCP"; if (fus_dat3.cn56xx.bar2_en) suffix = "NSPB2"; } if (fus3.cn56xx.crip_1024k) family = "54"; else family = "56"; } break; case 6: /* CN50XX */ family = "50"; break; case 7: /* CN52XX */ if (fus3.cn52xx.crip_256k) family = "51"; else family = "52"; break; case 0x93: /* CN61XX/CN60XX */ family = "61"; if (fus_dat3.cn63xx.l2c_crip == 2) family = "60"; if (fus_dat3.cn61xx.nozip) suffix = "SCP"; else suffix = "AAP"; break; case 0x90: /* CN63XX/CN62XX */ family = "63"; if (fus_dat3.s.l2c_crip == 2) family = "62"; if (num_cores == 6) /* Other core counts match generic */ core_model = "35"; if (fus_dat2.cn63xx.nocrypto) suffix = "CP"; else if (fus_dat2.cn63xx.dorm_crypto) suffix = "DAP"; else if (fus_dat3.cn63xx.nozip) suffix = "SCP"; else suffix = "AAP"; break; case 0x92: /* CN66XX */ family = "66"; if (num_cores == 6) /* Other core counts match generic */ core_model = "35"; if (fus_dat2.cn66xx.nocrypto && fus_dat2.cn66xx.dorm_crypto) suffix = "AP"; if (fus_dat2.cn66xx.nocrypto) suffix = "CP"; else if (fus_dat2.cn66xx.dorm_crypto) suffix = "DAP"; else if (fus_dat3.cn66xx.nozip && fus_dat2.cn66xx.raid_en) suffix = "SCP"; else if (!fus_dat2.cn66xx.raid_en) suffix = "HAP"; else suffix = "AAP"; break; case 0x91: /* CN68XX */ family = "68"; if (fus_dat2.cn68xx.nocrypto && fus_dat3.cn68xx.nozip) suffix = "CP"; else if (fus_dat2.cn68xx.dorm_crypto) suffix = "DAP"; else if (fus_dat3.cn68xx.nozip) suffix = "SCP"; else if (fus_dat2.cn68xx.nocrypto) suffix = "SP"; else if (!fus_dat2.cn68xx.raid_en) suffix = "HAP"; else suffix = "AAP"; break; case 0x94: /* CNF71XX */ family = "F71"; if (fus_dat3.cnf71xx.nozip) suffix = "SCP"; else suffix = "AAP"; break; case 0x95: /* CN78XX */ family = "78"; if (fus_dat3.cn70xx.nozip) suffix = "SCP"; else suffix = "AAP"; break; case 0x96: /* CN70XX */ family = "70"; if (cvmx_read_csr(CVMX_MIO_FUS_PDF) & (0x1ULL << 32)) family = "71"; if (fus_dat2.cn70xx.nocrypto) suffix = "CP"; else if (fus_dat3.cn70xx.nodfa_dte) suffix = "SCP"; else suffix = "AAP"; break; default: family = "XX"; core_model = "XX"; strcpy(pass, "X.X"); suffix = "XXX"; break; } #ifndef CVMX_BUILD_FOR_UBOOT clock_mhz = cvmx_clock_get_rate(CVMX_CLOCK_RCLK) / 1000000; #endif if (family[0] != '3') { if (OCTEON_IS_OCTEON1PLUS() || OCTEON_IS_OCTEON2()) { int fuse_base = 384 / 8; if (family[0] == '6' || OCTEON_IS_OCTEON3()) fuse_base = 832 / 8; /* Check for model in fuses, overrides normal decode */ /* This is _not_ valid for Octeon CN3XXX models */ fuse_data |= cvmx_fuse_read_byte(fuse_base + 5); fuse_data = fuse_data << 8; fuse_data |= cvmx_fuse_read_byte(fuse_base + 4); fuse_data = fuse_data << 8; fuse_data |= cvmx_fuse_read_byte(fuse_base + 3); fuse_data = fuse_data << 8; fuse_data |= cvmx_fuse_read_byte(fuse_base + 2); fuse_data = fuse_data << 8; fuse_data |= cvmx_fuse_read_byte(fuse_base + 1); fuse_data = fuse_data << 8; fuse_data |= cvmx_fuse_read_byte(fuse_base); if (fuse_data & 0x7ffff) { int model = fuse_data & 0x3fff; int suffix = (fuse_data >> 14) & 0x1f; if (suffix && model) { /* Have both number and suffix in fuses, so both */ sprintf(fuse_model, "%d%c", model, 'A' + suffix - 1); core_model = ""; family = fuse_model; } else if (suffix && !model) { /* Only have suffix, so add suffix to 'normal' model number */ sprintf(fuse_model, "%s%c", core_model, 'A' + suffix - 1); core_model = fuse_model; } else { /* Don't have suffix, so just use model from fuses */ sprintf(fuse_model, "%d", model); core_model = ""; family = fuse_model; } } } else {
void init_octeon_pcie(void) { int first_busno; int i; int rc = 0; int node = cvmx_get_node_num(); struct pci_controller *hose; int pcie_port; first_busno = OCTEON_FIRST_PCIE_BUSNO; memset(&hose_pcie[0], 0, sizeof(hose_pcie[0]) * num_pcie_ports); debug("Starting PCIE on node %d\n", node); for (i = 0; i < num_pcie_ports; i++) { pcie_port = ((node << 4) | i); rc = cvmx_pcie_rc_initialize(pcie_port); if (rc != 0) continue; mdelay(1000); /* Should delay 1 second according to standard */ hose = &hose_pcie[i]; hose->priv_data = (void *)&oct_pcie_data[i]; oct_pcie_data[i].pcie_port = pcie_port;; hose->config_table = pci_board_config_table; hose->first_busno = first_busno; hose->last_busno = 0xff; /* PCI I/O space (Sub-DID == 2) */ pci_set_region(hose->regions + 0, octeon_pcie_region_info[i].io_base, octeon_pcie_region_info[i].io_base, octeon_pcie_region_info[i].io_size, PCI_REGION_IO); /* PCI memory space (Sub-DID == 3) */ pci_set_region(hose->regions + 1, octeon_pcie_region_info[i].mem_base, octeon_pcie_region_info[i].mem_base, octeon_pcie_region_info[i].mem_size, PCI_REGION_MEM); hose->region_count = 2; pci_set_ops(hose, octeon_pcie_read_config_byte, octeon_pcie_read_config_word, octeon_pcie_read_config_dword, octeon_pcie_write_config_byte, octeon_pcie_write_config_word, octeon_pcie_write_config_dword); pci_register_hose(hose); hose->last_busno = pci_hose_scan(hose); debug("PCIe: port=%d, first_bus=%d, last_bus=%d,\n\t" "mem_base=0x%x, mem_size=0x%x, io_base=0x%x, io_size=0x%x\n", octeon_get_pcie_port(hose), hose->first_busno, hose->last_busno, octeon_pcie_region_info[i].mem_base, octeon_pcie_region_info[i].mem_size, octeon_pcie_region_info[i].io_base, octeon_pcie_region_info[i].io_size); first_busno = hose->last_busno + 1; #if CONFIG_OCTEON_PCI_ENABLE_32BIT_MAPPING if (OCTEON_IS_OCTEON2() || OCTEON_IS_OCTEON3()) { cvmx_pemx_bar_ctl_t bar_ctl; cvmx_pemx_bar1_indexx_t pemx_bar1_indexx; uint64_t bar_base; int j; /* Setup BAR1 to map bus address 0x0 to the base of * u-boot's TLB mapping. This allows us to have u-boot * located anywhere in memory (including above 32 bit * addressable space) and still have 32 bit PCI devices * have access to memory that is statically allocated * or malloced by u-boot, both of which are TLB mapped. */ cvmx_write_csr_node(node, CVMX_PEMX_P2N_BAR1_START(i), 0); /* Disable bar0/bar2, as we are not using them here */ cvmx_write_csr_node(node, CVMX_PEMX_P2N_BAR0_START(i), -1); cvmx_write_csr_node(node, CVMX_PEMX_P2N_BAR2_START(i), -1); /* Select 64 MByte mapping size for bar 1 on * all ports */ bar_ctl.u64 = cvmx_read_csr_node(node, CVMX_PEMX_BAR_CTL(i)); bar_ctl.s.bar1_siz = 1; /* 64MB */ bar_ctl.s.bar2_enb = 0; cvmx_write_csr_node(node, CVMX_PEMX_BAR_CTL(i), bar_ctl.u64); /* Configure the regions in bar 1 to map to the * DRAM used by u-boot. */ /* Round down to 4MByte boundary to meet BAR mapping * requirements */ bar_base = gd->bd->bi_uboot_ram_addr & ~0x3fffffull; debug("pcie: port %d, setting BAR base to 0x%llx\n", i, bar_base); pemx_bar1_indexx.u64 = 0; pemx_bar1_indexx.s.addr_v = 1; pemx_bar1_indexx.s.end_swp = 1; pemx_bar1_indexx.s.ca = 1; for (j = 0; j < 16; j++) { pemx_bar1_indexx.s.addr_idx = (bar_base + 4 * 1024 * 1024 * j) >> 22; cvmx_write64_uint64(CVMX_PEMX_BAR1_INDEXX(j, i), pemx_bar1_indexx.u64); } } #endif /* CONFIG_OCTEON_PCI_ENABLE_32BIT_MAPPING */ }