static int GetPSDData_8812( IN PDM_ODM_T pDM_Odm, unsigned int point, u1Byte initial_gain_psd) { int psd_report; struct rtl8192cd_priv *priv=pDM_Odm->priv; //Set DCO frequency index, offset=(40MHz/SamplePts)*point ODM_SetBBReg(pDM_Odm, 0x910, 0x3FF, point); //Start PSD calculation, Reg808[22]=0->1 ODM_SetBBReg(pDM_Odm, 0x910, BIT22, 1); //Need to wait for HW PSD report delay_us(priv->pshare->rf_ft_var.dfs_psd_delay); ODM_SetBBReg(pDM_Odm, 0x910, BIT22, 0); //Read PSD report, Reg8B4[15:0] psd_report = (int)ODM_GetBBReg(pDM_Odm,0xf44, bMaskDWord) & 0x0000FFFF; if(priv->pshare->rf_ft_var.psd_skip_lookup_table){ if(psd_report >=14) psd_report = 23; else psd_report = 8; } else{ psd_report = (int)(ConvertTo_dB((u4Byte)psd_report)); } return psd_report; }
VOID odm_SetCrystalCap( IN PVOID pDM_VOID, IN u1Byte CrystalCap ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); BOOLEAN bEEPROMCheck; #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) PADAPTER Adapter = pDM_Odm->Adapter; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); bEEPROMCheck = (pHalData->EEPROMVersion >= 0x01)?TRUE:FALSE; #else bEEPROMCheck = TRUE; #endif if(pCfoTrack->CrystalCap == CrystalCap) return; pCfoTrack->CrystalCap = CrystalCap; if (pDM_Odm->SupportICType & (ODM_RTL8188E | ODM_RTL8188F)) { /* write 0x24[22:17] = 0x24[16:11] = CrystalCap */ CrystalCap = CrystalCap & 0x3F; ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x007ff800, (CrystalCap|(CrystalCap << 6))); } else if (pDM_Odm->SupportICType & ODM_RTL8812) { /* write 0x2C[30:25] = 0x2C[24:19] = CrystalCap */ CrystalCap = CrystalCap & 0x3F; ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x7FF80000, (CrystalCap|(CrystalCap << 6))); } else if (((pDM_Odm->SupportICType & ODM_RTL8723A) && bEEPROMCheck) || (pDM_Odm->SupportICType & (ODM_RTL8703B|ODM_RTL8723B|ODM_RTL8192E|ODM_RTL8821))) { /* 0x2C[23:18] = 0x2C[17:12] = CrystalCap */ CrystalCap = CrystalCap & 0x3F; ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x00FFF000, (CrystalCap|(CrystalCap << 6))); } else if (pDM_Odm->SupportICType & ODM_RTL8821B) { /* write 0x28[6:1] = 0x24[30:25] = CrystalCap */ CrystalCap = CrystalCap & 0x3F; ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x7E000000, CrystalCap); ODM_SetBBReg(pDM_Odm, REG_AFE_PLL_CTRL, 0x7E, CrystalCap); } else if (pDM_Odm->SupportICType & ODM_RTL8814A) { /* write 0x2C[26:21] = 0x2C[20:15] = CrystalCap */ CrystalCap = CrystalCap & 0x3F; ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x07FF8000, (CrystalCap|(CrystalCap << 6))); } else if (pDM_Odm->SupportICType & ODM_RTL8822B) { /* write 0x24[30:25] = 0x28[6:1] = CrystalCap */ CrystalCap = CrystalCap & 0x3F; ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x7e000000, CrystalCap); ODM_SetBBReg(pDM_Odm, REG_AFE_PLL_CTRL, 0x7e, CrystalCap); } else { ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_SetCrystalCap(): Use default setting.\n")); ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap|(CrystalCap << 6))); } ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_SetCrystalCap(): CrystalCap = 0x%x\n", CrystalCap)); #endif }
VOID odm_1R_CCA( IN PVOID pDM_VOID ) { PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable; if(pDM_Odm->RSSI_Min!= 0xFF) { if(pDM_PSTable->PreCCAState == CCA_2R) { if(pDM_Odm->RSSI_Min >= 35) pDM_PSTable->CurCCAState = CCA_1R; else pDM_PSTable->CurCCAState = CCA_2R; } else{ if(pDM_Odm->RSSI_Min <= 30) pDM_PSTable->CurCCAState = CCA_2R; else pDM_PSTable->CurCCAState = CCA_1R; } } else{ pDM_PSTable->CurCCAState=CCA_MAX; } if(pDM_PSTable->PreCCAState != pDM_PSTable->CurCCAState) { if(pDM_PSTable->CurCCAState == CCA_1R) { if( pDM_Odm->RFType ==ODM_2T2R ) { ODM_SetBBReg(pDM_Odm, 0xc04 , bMaskByte0, 0x13); //PHY_SetBBReg(pAdapter, 0xe70, bMaskByte3, 0x20); } else { ODM_SetBBReg(pDM_Odm, 0xc04 , bMaskByte0, 0x23); //PHY_SetBBReg(pAdapter, 0xe70, 0x7fc00000, 0x10c); // Set RegE70[30:22] = 9b'100001100 } } else { ODM_SetBBReg(pDM_Odm, 0xc04 , bMaskByte0, 0x33); //PHY_SetBBReg(pAdapter,0xe70, bMaskByte3, 0x63); } pDM_PSTable->PreCCAState = pDM_PSTable->CurCCAState; } //ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, ("CCAStage = %s\n",(pDM_PSTable->CurCCAState==0)?"1RCCA":"2RCCA")); }
VOID odm_1R_CCA( IN PVOID pDM_VOID ) { PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable; if(pDM_Odm->RSSI_Min!= 0xFF) { if(pDM_PSTable->PreCCAState == CCA_2R) { if(pDM_Odm->RSSI_Min >= 35) pDM_PSTable->CurCCAState = CCA_1R; else pDM_PSTable->CurCCAState = CCA_2R; } else{ if(pDM_Odm->RSSI_Min <= 30) pDM_PSTable->CurCCAState = CCA_2R; else pDM_PSTable->CurCCAState = CCA_1R; } } else{ pDM_PSTable->CurCCAState=CCA_MAX; } if(pDM_PSTable->PreCCAState != pDM_PSTable->CurCCAState) { if(pDM_PSTable->CurCCAState == CCA_1R) { if( pDM_Odm->RFType ==ODM_2T2R ) { ODM_SetBBReg(pDM_Odm, 0xc04 , bMaskByte0, 0x13); //PHY_SetBBReg(pAdapter, 0xe70, bMaskByte3, 0x20); } else { ODM_SetBBReg(pDM_Odm, 0xc04 , bMaskByte0, 0x23); //PHY_SetBBReg(pAdapter, 0xe70, 0x7fc00000, 0x10c); // Set RegE70[30:22] = 9b'100001100 } } else { ODM_SetBBReg(pDM_Odm, 0xc04 , bMaskByte0, 0x33); //PHY_SetBBReg(pAdapter,0xe70, bMaskByte3, 0x63); } pDM_PSTable->PreCCAState = pDM_PSTable->CurCCAState; } }
VOID Phydm_SetTRxMux( IN PVOID pDM_VOID, IN PhyDM_Trx_MUX_Type txMode, IN PhyDM_Trx_MUX_Type rxMode ) { PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT3|BIT2|BIT1, txMode); // set TXmod to standby mode to remove outside noise affect ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT22|BIT21|BIT20, rxMode); // set RXmod to standby mode to remove outside noise affect if(pDM_Odm->RFType > ODM_1T1R) { ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT3|BIT2|BIT1, txMode); // set TXmod to standby mode to remove outside noise affect ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT22|BIT21|BIT20, rxMode); // set RXmod to standby mode to remove outside noise affect } } else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT11|BIT10|BIT9|BIT8, txMode); // set TXmod to standby mode to remove outside noise affect ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT7|BIT6|BIT5|BIT4, rxMode); // set RXmod to standby mode to remove outside noise affect if(pDM_Odm->RFType > ODM_1T1R) { ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT11|BIT10|BIT9|BIT8, txMode); // set TXmod to standby mode to remove outside noise affect ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT7|BIT6|BIT5|BIT4, rxMode); // set RXmod to standby mode to remove outside noise affect } } }
VOID odm_DynamicPacketdetectionTH_8821A( IN PDM_ODM_T pDM_Odm ) { if (pDM_Odm->SupportICType & ODM_RTL8821) { if (pDM_Odm->RSSI_Min <= 25) { ODM_SetBBReg(pDM_Odm, rPwed_TH_Jaguar, bMaskDWord, 0x2aaaf1a8); ODM_SetBBReg(pDM_Odm, rBWIndication_Jaguar, BIT26, 1); } else if (pDM_Odm->RSSI_Min >= 30) { ODM_SetBBReg(pDM_Odm, rPwed_TH_Jaguar, bMaskDWord, 0x2aaaeec8); ODM_SetBBReg(pDM_Odm, rBWIndication_Jaguar, BIT26, 0); } } }
VOID halTxbf8192E_RfMode( IN PVOID pDM_VOID, IN PRT_BEAMFORMING_INFO pBeamInfo ) { PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; BOOLEAN bSelfBeamformer = FALSE; BOOLEAN bSelfBeamformee = FALSE; BEAMFORMING_CAP BeamformCap = BEAMFORMING_CAP_NONE; ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); if (pDM_Odm->RFType == ODM_1T1R) return; ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); /*RF Mode table write enable*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, 0x80000, 0x1); /*RF Mode table write enable*/ if (pBeamInfo->beamformee_su_cnt > 0) { /*Path_A*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode 0x30=0x18000*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0x77fc2); /*Enable TXIQGEN in RX mode*/ /*Path_B*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0x77fc2); /*Enable TXIQGEN in RX mode*/ } else { /*Path_A*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0x77f82); /*Disable TXIQGEN in RX mode*/ /*Path_B*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0x77f82); /*Disable TXIQGEN in RX mode*/ } ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); /*RF Mode table write disable*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, 0x80000, 0x0); /*RF Mode table write disable*/ if (pBeamInfo->beamformee_su_cnt > 0) { ODM_SetBBReg(pDM_Odm, rFPGA1_TxInfo, bMaskDWord, 0x83321333); ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, bMaskByte3, 0xc1); } else ODM_SetBBReg(pDM_Odm, rFPGA1_TxInfo, bMaskDWord, 0x81121313); }
VOID odm_SetCrystalCap( IN PVOID pDM_VOID, IN u1Byte CrystalCap ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); BOOLEAN bEEPROMCheck; #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) PADAPTER Adapter = pDM_Odm->Adapter; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); bEEPROMCheck = (pHalData->EEPROMVersion >= 0x01)?TRUE:FALSE; #else bEEPROMCheck = TRUE; #endif if(pCfoTrack->CrystalCap == CrystalCap) return; pCfoTrack->CrystalCap = CrystalCap; if(pDM_Odm->SupportICType & ODM_RTL8192D) { ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x000000F0, CrystalCap & 0x0F); ODM_SetBBReg(pDM_Odm, REG_AFE_PLL_CTRL, 0xF0000000, ((CrystalCap & 0xF0) >> 4)); }
void odm_ConfigBB_PHY_8812A( IN PDM_ODM_T pDM_Odm, IN u4Byte Addr, IN u4Byte Bitmask, IN u4Byte Data ) { if (Addr == 0xfe) { #ifdef CONFIG_LONG_DELAY_ISSUE ODM_sleep_ms(50); #else ODM_delay_ms(50); #endif } else if (Addr == 0xfd) { ODM_delay_ms(5); } else if (Addr == 0xfc) { ODM_delay_ms(1); } else if (Addr == 0xfb) { ODM_delay_us(50); } else if (Addr == 0xfa) { ODM_delay_us(5); } else if (Addr == 0xf9) { ODM_delay_us(1); } else { ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); // Add 1us delay between BB/RF register setting. ODM_delay_us(1); } ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); }
void odm_ConfigBB_PHY_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data) { if (Addr == 0xfe) { ODM_sleep_ms(50); } else if (Addr == 0xfd) { ODM_delay_ms(5); } else if (Addr == 0xfc) { ODM_delay_ms(1); } else if (Addr == 0xfb) { ODM_delay_us(50); } else if (Addr == 0xfa) { ODM_delay_us(5); } else if (Addr == 0xf9) { ODM_delay_us(1); } else { if (Addr == 0xa24) pDM_Odm->RFCalibrateInfo.RegA24 = Data; ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); /* Add 1us delay between BB/RF register setting. */ ODM_delay_us(1); ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); } }
VOID _LOK_One_Shot( IN PVOID pDM_VOID ) { PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; PIQK_INFO pIQK_info = &pDM_Odm->IQK_info; u1Byte Path = 0, delay_count = 0, ii; BOOLEAN LOK_notready = FALSE; u4Byte LOK_temp1 = 0, LOK_temp2 = 0; ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("============ LOK ============\n")); for(Path =0; Path <=3; Path++){ ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("==========S%d LOK ==========\n", Path)); ODM_SetBBReg(pDM_Odm, 0x9a4, BIT(21)|BIT(20), Path); // ADC Clock source ODM_Write4Byte(pDM_Odm, 0x1b00, (0xf8000001|(1<<(4+Path)))); // LOK: CMD ID = 0 {0xf8000011, 0xf8000021, 0xf8000041, 0xf8000081} ODM_delay_ms(LOK_delay); delay_count = 0; LOK_notready = TRUE; while(LOK_notready){ LOK_notready = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0x1b00, BIT(0)); ODM_delay_ms(1); delay_count++; if(delay_count >= 10){ ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("S%d LOK timeout!!!\n", Path)); _IQK_ResetNCTL_8814A(pDM_Odm); break; } } ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("S%d ==> delay_count = 0x%d\n", Path, delay_count)); if(!LOK_notready){ ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000000|(Path<<1)); ODM_Write4Byte(pDM_Odm, 0x1bd4, 0x003f0001); LOK_temp2 = (ODM_GetBBReg(pDM_Odm, 0x1bfc, 0x003e0000)+0x10)&0x1f; LOK_temp1 = (ODM_GetBBReg(pDM_Odm, 0x1bfc, 0x0000003e)+0x10)&0x1f; for(ii = 1; ii<5; ii++){ LOK_temp1 = LOK_temp1 + ((LOK_temp1 & BIT(4-ii))<<(ii*2)); LOK_temp2 = LOK_temp2 + ((LOK_temp2 & BIT(4-ii))<<(ii*2)); } ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("LOK_temp1 = 0x%x, LOK_temp2 = 0x%x\n", LOK_temp1>>4, LOK_temp2>>4)); ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)Path, 0x8, 0x07c00, LOK_temp1>>4); ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)Path, 0x8, 0xf8000, LOK_temp2>>4); ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("==>S%d fill LOK\n", Path)); } else{
VOID ODM_PathDiversityInit_8812A( IN PDM_ODM_T pDM_Odm ) { u4Byte i; pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv; ODM_SetBBReg(pDM_Odm, 0x80c , BIT29, 1); //Tx path from Reg ODM_SetBBReg(pDM_Odm, 0x80c , 0xFFF0, 0x111); //Tx by Reg ODM_SetBBReg(pDM_Odm, 0x6d8 , BIT7|BIT6, 1); //Resp Tx by Txinfo odm_UpdateTxPath_8812A(pDM_Odm, ODM_RF_PATH_A); for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++) { pDM_PathDiv->PathSel[i] = 1; // TxInfo default at path-A } }
VOID Phydm_NHMCounterStatisticsReset( IN PVOID pDM_VOID ) { PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 0); ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 1); } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 0); ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 1); } }
VOID halTxbf8821B_RfMode( IN PVOID pDM_VOID, IN PRT_BEAMFORMING_INFO pBeamInfo ) { PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; if (pDM_Odm->RFType == ODM_1T1R) return; ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] set TxIQGen\n", __func__)); ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WeLut_Jaguar, 0x80000, 0x1); /*RF Mode table write enable*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WeLut_Jaguar, 0x80000, 0x1); /*RF Mode table write enable*/ if (pBeamInfo->beamformee_su_cnt > 0) { /*Path_A*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/ /*Path_B*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/ } else { /*Path_A*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xC26BF); /*Disable TXIQGEN in RX mode*/ /*Path_B*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0xC26BF); /*Disable TXIQGEN in RX mode*/ } ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WeLut_Jaguar, 0x80000, 0x0); /*RF Mode table write disable*/ ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WeLut_Jaguar, 0x80000, 0x0); /*RF Mode table write disable*/ if (pBeamInfo->beamformee_su_cnt > 0) ODM_SetBBReg(pDM_Odm, rTxPath_Jaguar, bMaskByte1, 0x33); else ODM_SetBBReg(pDM_Odm, rTxPath_Jaguar, bMaskByte1, 0x11); }
VOID _IQK_ConfigureMAC_8814A( IN PDM_ODM_T pDM_Odm ) { // ========MAC register setting======== ODM_Write1Byte(pDM_Odm, 0x522, 0x3f); ODM_SetBBReg(pDM_Odm, 0x550, BIT(11)|BIT(3), 0x0); ODM_Write1Byte(pDM_Odm, 0x808, 0x00); // RX ante off ODM_SetBBReg(pDM_Odm, 0x838, 0xf, 0xe); // CCA off ODM_SetBBReg(pDM_Odm, 0xa14, BIT(9)|BIT(8), 0x3); // CCK RX Path off ODM_Write4Byte(pDM_Odm, 0xcb0, 0x77777777); ODM_Write4Byte(pDM_Odm, 0xeb0, 0x77777777); ODM_Write4Byte(pDM_Odm, 0x18b4, 0x77777777); ODM_Write4Byte(pDM_Odm, 0x1ab4, 0x77777777); ODM_SetBBReg(pDM_Odm, 0x1abc, 0x0ff00000, 0x77); //by YN ODM_SetBBReg(pDM_Odm, 0xcbc, 0xf, 0x0); }
void odm_ConfigBB_AGC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data) { ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); /* Add 1us delay between BB/RF register setting. */ ODM_delay_us(1); ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); }
VOID _IQK_AFESetting_8814A( IN PDM_ODM_T pDM_Odm, IN BOOLEAN Do_IQK ) { if(Do_IQK) { // IQK AFE Setting RX_WAIT_CCA mode ODM_Write4Byte(pDM_Odm, 0xc60, 0x0e808003); ODM_Write4Byte(pDM_Odm, 0xe60, 0x0e808003); ODM_Write4Byte(pDM_Odm, 0x1860, 0x0e808003); ODM_Write4Byte(pDM_Odm, 0x1a60, 0x0e808003); ODM_SetBBReg(pDM_Odm, 0x90c, BIT(13), 0x1); ODM_SetBBReg(pDM_Odm, 0x764, BIT(10)|BIT(9), 0x3); ODM_SetBBReg(pDM_Odm, 0x764, BIT(10)|BIT(9), 0x0); ODM_SetBBReg(pDM_Odm, 0x804, BIT(2), 0x1); ODM_SetBBReg(pDM_Odm, 0x804, BIT(2), 0x0); ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AFE IQK mode Success!!!!\n")); } else { ODM_Write4Byte(pDM_Odm, 0xc60, 0x07808003); ODM_Write4Byte(pDM_Odm, 0xe60, 0x07808003); ODM_Write4Byte(pDM_Odm, 0x1860, 0x07808003); ODM_Write4Byte(pDM_Odm, 0x1a60, 0x07808003); ODM_SetBBReg(pDM_Odm, 0x90c, BIT(13), 0x1); ODM_SetBBReg(pDM_Odm, 0x764, BIT(10)|BIT(9), 0x3); ODM_SetBBReg(pDM_Odm, 0x764, BIT(10)|BIT(9), 0x0); ODM_SetBBReg(pDM_Odm, 0x804, BIT(2), 0x1); ODM_SetBBReg(pDM_Odm, 0x804, BIT(2), 0x0); ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AFE Normal mode Success!!!!\n")); } }
VOID Phydm_SetEDCCAThreshold( IN PVOID pDM_VOID, IN s1Byte H2L, IN s1Byte L2H ) { PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte0, (u1Byte)L2H); ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte2, (u1Byte)H2L); } else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskByte0, (u1Byte)L2H); ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskByte1, (u1Byte)H2L); } }
VOID phydm_NHMtrigger( IN PVOID pDM_VOID ) { PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { /*Trigger NHM*/ ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 0); ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 1); } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { /*Trigger NHM*/ ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 0); ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 1); } }
VOID Phydm_NHMCounterStatisticsInit( IN PVOID pDM_VOID ) { PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { /*PHY parameters initialize for n series*/ ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N + 2, 0xC350); /*0x894[31:16]=0x0xC350 Time duration for NHM unit: us, 0xc350=200ms*/ ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N + 2, 0xffff); /*0x890[31:16]=0xffff th_9, th_10*/ ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff50); /*0x898=0xffffff52 th_3, th_2, th_1, th_0*/ ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff); /*0x89c=0xffffffff th_7, th_6, th_5, th_4*/ ODM_SetBBReg(pDM_Odm, ODM_REG_FPGA0_IQK_11N, bMaskByte0, 0xff); /*0xe28[7:0]=0xff th_8*/ ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10 | BIT9 | BIT8, 0x1); /*0x890[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/ ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT7, 0x1); /*0xc0c[7]=1 max power among all RX ants*/ } #if (RTL8195A_SUPPORT == 0) else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { /*PHY parameters initialize for ac series*/ ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11AC + 2, 0xC350); /*0x990[31:16]=0xC350 Time duration for NHM unit: us, 0xc350=200ms*/ ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC + 2, 0xffff); /*0x994[31:16]=0xffff th_9, th_10*/ ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff50); /*0x998=0xffffff52 th_3, th_2, th_1, th_0*/ ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff); /*0x99c=0xffffffff th_7, th_6, th_5, th_4*/ ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, 0xff); /*0x9a0[7:0]=0xff th_8*/ ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8 | BIT9 | BIT10, 0x1); /*0x994[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/ ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_9E8_11AC, BIT0, 0x1); /*0x9e8[7]=1 max power among all RX ants*/ } #endif }
VOID ODM_UpdateRxIdleAnt_88E(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant) { pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; u4Byte DefaultAnt, OptionalAnt; if(pDM_FatTable->RxIdleAnt != Ant) { ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Update Rx Idle Ant\n")); if(Ant == MAIN_ANT) { DefaultAnt = (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)?MAIN_ANT_CG_TRX:MAIN_ANT_CGCS_RX; OptionalAnt = (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)?AUX_ANT_CG_TRX:AUX_ANT_CGCS_RX; } else { DefaultAnt = (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)?AUX_ANT_CG_TRX:AUX_ANT_CGCS_RX; OptionalAnt = (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)?MAIN_ANT_CG_TRX:MAIN_ANT_CGCS_RX; } if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) { ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); //Default RX ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); //Optional RX ODM_SetBBReg(pDM_Odm, ODM_REG_ANTSEL_CTRL_11N , BIT14|BIT13|BIT12, DefaultAnt); //Default TX ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11N , BIT6|BIT7, DefaultAnt); //Resp Tx } else if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) { ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); //Default RX ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); //Optional RX } } pDM_FatTable->RxIdleAnt = Ant; ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("RxIdleAnt=%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); printk("RxIdleAnt=%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"); }
void odm_ConfigBB_AGC_8812A( IN PDM_ODM_T pDM_Odm, IN u4Byte Addr, IN u4Byte Bitmask, IN u4Byte Data ) { ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); // Add 1us delay between BB/RF register setting. ODM_delay_us(1); ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); }
void odm_ConfigBB_AGC_8723A( PDM_ODM_T pDM_Odm, u32 Addr, u32 Bitmask, u32 Data ) { ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); // Add 1us delay between BB/RF register setting. ODM_delay_us(1); ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); }
VOID odm_UpdateTxPath_8812A(IN PDM_ODM_T pDM_Odm, IN u1Byte Path) { pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv; if(pDM_PathDiv->RespTxPath != Path) { ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Need to Update Tx Path\n")); if(Path == ODM_RF_PATH_A) { ODM_SetBBReg(pDM_Odm, 0x80c , 0xFFF0, 0x111); //Tx by Reg ODM_SetBBReg(pDM_Odm, 0x6d8 , BIT7|BIT6, 1); //Resp Tx by Txinfo } else { ODM_SetBBReg(pDM_Odm, 0x80c , 0xFFF0, 0x222); //Tx by Reg ODM_SetBBReg(pDM_Odm, 0x6d8 , BIT7|BIT6, 2); //Resp Tx by Txinfo } } pDM_PathDiv->RespTxPath = Path; ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Path=%s\n",(Path==ODM_RF_PATH_A)?"ODM_RF_PATH_A":"ODM_RF_PATH_B")); }
VOID odm_RX_HWAntDivInit( IN PDM_ODM_T pDM_Odm ) { u4Byte value32; PADAPTER Adapter = pDM_Odm->Adapter; #if (MP_DRIVER == 1) if (*(pDM_Odm->mp_mode) == 1) { pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV; ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); // 1:CG, 0:CS return; } #endif ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_RX_HWAntDivInit() \n")); //MAC Setting value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output //Pin Settings ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 1); //Regb2c[22]=1'b0 //disable CS/CG switch ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only //OFDM Settings ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0); //CCK Settings ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT); ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , 0xFFFF, 0x0201); //antenna mapping table //ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //Enable HW AntDiv //ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, 1); //Enable CCK AntDiv }
VOID odm_SetATCStatus( IN PVOID pDM_VOID, IN BOOLEAN ATCStatus ) { PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); if(pCfoTrack->bATCStatus == ATCStatus) return; ODM_SetBBReg(pDM_Odm, ODM_REG(BB_ATC,pDM_Odm), ODM_BIT(BB_ATC,pDM_Odm), ATCStatus); pCfoTrack->bATCStatus = ATCStatus; }
VOID odm_PHY_ReloadAFERegisters( IN PVOID pDM_VOID, IN pu4Byte AFEReg, IN pu4Byte AFEBackup, IN u4Byte RegiesterNum ) { PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; u4Byte i; //RT_DISP(FINIT, INIT_IQK, ("Reload ADDA power saving parameters !\n")); for(i = 0 ; i < RegiesterNum; i++) { ODM_SetBBReg(pDM_Odm, AFEReg[i], bMaskDWord, AFEBackup[i]); } }
VOID odm_AdaptivityInit( IN PDM_ODM_T pDM_Odm ) { #ifdef CONFIG_ODM_ADAPTIVITY if(pDM_Odm->SupportICType == ODM_RTL8723B) { pDM_Odm->TH_L2H_ini = 0xf8; // -8 } if((pDM_Odm->SupportICType == ODM_RTL8192E)&&(pDM_Odm->SupportInterface == ODM_ITRF_PCIE)) { pDM_Odm->TH_L2H_ini = 0xf0; // -16 } else { pDM_Odm->TH_L2H_ini = 0xf7; // -9 } pDM_Odm->TH_EDCCA_HL_diff = 7; pDM_Odm->IGI_Base = 0x32; pDM_Odm->IGI_target = 0x1c; pDM_Odm->ForceEDCCA = 0; pDM_Odm->AdapEn_RSSI = 20; pDM_Odm->NHM_disable = _FALSE; pDM_Odm->TxHangFlg = _TRUE; pDM_Odm->txEdcca0 = 0; pDM_Odm->txEdcca1 = 0; pDM_Odm->H2L_lb= 0; pDM_Odm->L2H_lb= 0; pDM_Odm->Adaptivity_IGI_upper = 0; odm_NHMBBInit(pDM_Odm); //Reg524[11]=0 is easily to transmit packets during adaptivity test ODM_SetBBReg(pDM_Odm, REG_RD_CTRL, BIT11, 1); // stop counting if EDCCA is asserted #endif /* CONFIG_ODM_ADAPTIVITY */ }
VOID odm_NHMBBInit( IN PVOID pDM_VOID ) { PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; pDM_Odm->adaptivity_flag = 0; pDM_Odm->tolerance_cnt = 3; pDM_Odm->NHMLastTxOkcnt = 0; pDM_Odm->NHMLastRxOkcnt = 0; pDM_Odm->NHMCurTxOkcnt = 0; pDM_Odm->NHMCurRxOkcnt = 0; if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { //PHY parameters initialize for ac series ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11AC+2, 0x2710); //0x990[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC+2, 0xffff); //0x994[31:16]=0xffff th_9, th_10 //ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff5c); //0x998=0xffffff5c th_3, th_2, th_1, th_0 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff52); //0x998=0xffffff52 th_3, th_2, th_1, th_0 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff); //0x99c=0xffffffff th_7, th_6, th_5, th_4 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, 0xff); //0x9a0[7:0]=0xff th_8 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8|BIT9|BIT10, 7); //0x994[9:8]=3 enable CCX ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_9E8_11AC, BIT0, 1); //0x9e8[7]=1 max power among all RX ants //panic_printk("RTL8812AU phy parameters init %s,%d\n", __FUNCTION__, __LINE__); } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { //PHY parameters initialize for n series ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N+2, 0x2710); //0x894[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms //ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N+2, 0x4e20); //0x894[31:16]=0x4e20 Time duration for NHM unit: 4us, 0x4e20=80ms ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N+2, 0xffff); //0x890[31:16]=0xffff th_9, th_10 //ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff5c); //0x898=0xffffff5c th_3, th_2, th_1, th_0 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff52); //0x898=0xffffff52 th_3, th_2, th_1, th_0 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff); //0x89c=0xffffffff th_7, th_6, th_5, th_4 ODM_SetBBReg(pDM_Odm, ODM_REG_FPGA0_IQK_11N, bMaskByte0, 0xff); //0xe28[7:0]=0xff th_8 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 7); //0x890[9:8]=3 enable CCX ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT7, 1); //0xc0c[7]=1 max power among all RX ants } }
VOID odm_TRX_HWAntDivInit( IN PDM_ODM_T pDM_Odm ) { u4Byte value32; PADAPTER Adapter = pDM_Odm->Adapter; #if (MP_DRIVER == 1) if (*(pDM_Odm->mp_mode) == 1) { pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV; ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); //Default RX (0/1) return; } #endif ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_TRX_HWAntDivInit() \n")); //MAC Setting value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output //Pin Settings ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only //OFDM Settings ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0); //CCK Settings ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples //Tx Settings ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); //Reg80c[21]=1'b0 //from TX Reg ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT); //antenna mapping table if(!pDM_Odm->bIsMPChip) //testchip { ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001 ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010 } else //MPchip ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , bMaskDWord, 0x0201); //Reg914=3'b010, Reg915=3'b001 //ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //Enable HW AntDiv //ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, 1); //Enable CCK AntDiv }