VOID
_LOK_One_Shot(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PIQK_INFO pIQK_info = &pDM_Odm->IQK_info;
u1Byte Path = 0, delay_count = 0, ii;
BOOLEAN LOK_notready = FALSE;
u4Byte LOK_temp1 = 0, LOK_temp2 = 0;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("============ LOK ============\n"));
for(Path =0; Path <=3; Path++){
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
("==========S%d LOK ==========\n", Path));
ODM_SetBBReg(pDM_Odm, 0x9a4, BIT(21)|BIT(20), Path); // ADC Clock source
ODM_Write4Byte(pDM_Odm, 0x1b00, (0xf8000001|(1<<(4+Path)))); // LOK: CMD ID = 0 {0xf8000011, 0xf8000021, 0xf8000041, 0xf8000081}
ODM_delay_ms(LOK_delay);
delay_count = 0;
LOK_notready = TRUE;
while(LOK_notready){
LOK_notready = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0x1b00, BIT(0));
ODM_delay_ms(1);
delay_count++;
if(delay_count >= 10){
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
("S%d LOK timeout!!!\n", Path));
_IQK_ResetNCTL_8814A(pDM_Odm);
break;
}
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
("S%d ==> delay_count = 0x%d\n", Path, delay_count));
if(!LOK_notready){
ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000000|(Path<<1));
ODM_Write4Byte(pDM_Odm, 0x1bd4, 0x003f0001);
LOK_temp2 = (ODM_GetBBReg(pDM_Odm, 0x1bfc, 0x003e0000)+0x10)&0x1f;
LOK_temp1 = (ODM_GetBBReg(pDM_Odm, 0x1bfc, 0x0000003e)+0x10)&0x1f;
for(ii = 1; ii<5; ii++){
LOK_temp1 = LOK_temp1 + ((LOK_temp1 & BIT(4-ii))<<(ii*2));
LOK_temp2 = LOK_temp2 + ((LOK_temp2 & BIT(4-ii))<<(ii*2));
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
("LOK_temp1 = 0x%x, LOK_temp2 = 0x%x\n", LOK_temp1>>4, LOK_temp2>>4));
ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)Path, 0x8, 0x07c00, LOK_temp1>>4);
ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)Path, 0x8, 0xf8000, LOK_temp2>>4);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
("==>S%d fill LOK\n", Path));
}
else{
VOID
_IQK_ResetNCTL_8814A(
IN PDM_ODM_T
pDM_Odm
)
{
ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000000);
ODM_Write4Byte(pDM_Odm, 0x1b80, 0x00000006);
ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000000);
ODM_Write4Byte(pDM_Odm, 0x1b80, 0x00000002);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ResetNCTL Success!!!!\n"))
}
VOID
HalTxbf8821B_Leave(
IN PVOID pDM_VOID,
IN u1Byte Idx
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo;
RT_BEAMFORMER_ENTRY BeamformerEntry;
RT_BEAMFORMEE_ENTRY BeamformeeEntry;
if (Idx < BEAMFORMER_ENTRY_NUM) {
BeamformerEntry = pBeamformingInfo->BeamformerEntry[Idx];
BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[Idx];
} else
return;
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Start!, IDx = %d\n", __func__, Idx));
/*Clear P_AID of Beamformee*/
/*Clear MAC address of Beamformer*/
/*Clear Associated Bfmee Sel*/
if (BeamformerEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) {
ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8821B, 0xC8);
if (Idx == 0) {
ODM_Write4Byte(pDM_Odm, REG_BFMER0_INFO_8812A, 0);
ODM_Write2Byte(pDM_Odm, REG_BFMER0_INFO_8812A + 4, 0);
ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8821B, 0);
ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8821B, 0);
ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8821B, 0);
} else {
ODM_Write4Byte(pDM_Odm, REG_BFMER1_INFO_8812A, 0);
ODM_Write2Byte(pDM_Odm, REG_BFMER1_INFO_8812A + 4, 0);
ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8821B, 0);
ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8821B, 0);
ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8821B, 0);
}
}
if (BeamformeeEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) {
halTxbf8821B_RfMode(pDM_Odm, pBeamformingInfo);
if (Idx == 0) {
ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8821B, 0x0);
ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A, 0);
} else {
ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8821B + 2, ODM_Read2Byte(pDM_Odm, REG_TXBF_CTRL_8821B + 2) & 0xF000);
ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 2, ODM_Read2Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 2) & 0x60);
}
}
}
VOID
HalTxbf8814A_Leave(
IN PVOID pDM_VOID,
IN u1Byte Idx
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo;
RT_BEAMFORMER_ENTRY BeamformerEntry;
RT_BEAMFORMEE_ENTRY BeamformeeEntry;
if (Idx < BEAMFORMER_ENTRY_NUM) {
BeamformerEntry = pBeamformingInfo->BeamformerEntry[Idx];
BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[Idx];
} else
return;
/*Clear P_AID of Beamformee*/
/*Clear MAC address of Beamformer*/
/*Clear Associated Bfmee Sel*/
if (BeamformerEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) {
ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8814A, 0xD8);
if (Idx == 0) {
ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8814A, 0);
ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8814A + 4, 0);
ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8814A, 0);
} else {
ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8814A, 0);
ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8814A + 4, 0);
ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8814A + 2, 0);
}
}
if (BeamformeeEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) {
halTxbf8814A_RfMode(pDM_Odm, pBeamformingInfo, Idx);
if (Idx == 0) {
ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A, 0x0);
ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 3) | BIT4 | BIT6 | BIT7);
ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A, 0);
} else {
ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 2, 0x0 | BIT14 | BIT15 | BIT12);
ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, ODM_Read2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2) & 0x60);
}
}
}
VOID
odm_NHMBBInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
pDM_Odm->adaptivity_flag = 0;
pDM_Odm->tolerance_cnt = 3;
pDM_Odm->NHMLastTxOkcnt = 0;
pDM_Odm->NHMLastRxOkcnt = 0;
pDM_Odm->NHMCurTxOkcnt = 0;
pDM_Odm->NHMCurRxOkcnt = 0;
if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
{
//PHY parameters initialize for ac series
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11AC+2, 0x2710); //0x990[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC+2, 0xffff); //0x994[31:16]=0xffff th_9, th_10
//ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff5c); //0x998=0xffffff5c th_3, th_2, th_1, th_0
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff52); //0x998=0xffffff52 th_3, th_2, th_1, th_0
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff); //0x99c=0xffffffff th_7, th_6, th_5, th_4
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, 0xff); //0x9a0[7:0]=0xff th_8
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8|BIT9|BIT10, 7); //0x994[9:8]=3 enable CCX
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_9E8_11AC, BIT0, 1); //0x9e8[7]=1 max power among all RX ants
//panic_printk("RTL8812AU phy parameters init %s,%d\n", __FUNCTION__, __LINE__);
}
else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
{
//PHY parameters initialize for n series
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N+2, 0x2710); //0x894[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms
//ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N+2, 0x4e20); //0x894[31:16]=0x4e20 Time duration for NHM unit: 4us, 0x4e20=80ms
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N+2, 0xffff); //0x890[31:16]=0xffff th_9, th_10
//ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff5c); //0x898=0xffffff5c th_3, th_2, th_1, th_0
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff52); //0x898=0xffffff52 th_3, th_2, th_1, th_0
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff); //0x89c=0xffffffff th_7, th_6, th_5, th_4
ODM_SetBBReg(pDM_Odm, ODM_REG_FPGA0_IQK_11N, bMaskByte0, 0xff); //0xe28[7:0]=0xff th_8
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 7); //0x890[9:8]=3 enable CCX
ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT7, 1); //0xc0c[7]=1 max power among all RX ants
}
}
VOID
_IQK_ConfigureMAC_8814A(
IN PDM_ODM_T pDM_Odm
)
{
// ========MAC register setting========
ODM_Write1Byte(pDM_Odm, 0x522, 0x3f);
ODM_SetBBReg(pDM_Odm, 0x550, BIT(11)|BIT(3), 0x0);
ODM_Write1Byte(pDM_Odm, 0x808, 0x00); // RX ante off
ODM_SetBBReg(pDM_Odm, 0x838, 0xf, 0xe); // CCA off
ODM_SetBBReg(pDM_Odm, 0xa14, BIT(9)|BIT(8), 0x3); // CCK RX Path off
ODM_Write4Byte(pDM_Odm, 0xcb0, 0x77777777);
ODM_Write4Byte(pDM_Odm, 0xeb0, 0x77777777);
ODM_Write4Byte(pDM_Odm, 0x18b4, 0x77777777);
ODM_Write4Byte(pDM_Odm, 0x1ab4, 0x77777777);
ODM_SetBBReg(pDM_Odm, 0x1abc, 0x0ff00000, 0x77);
//by YN
ODM_SetBBReg(pDM_Odm, 0xcbc, 0xf, 0x0);
}
VOID
_IQK_RestoreMacBB_8814A(
IN PDM_ODM_T pDM_Odm,
IN pu4Byte MAC_backup,
IN pu4Byte BB_backup,
IN pu4Byte Backup_MAC_REG,
IN pu4Byte Backup_BB_REG
)
{
u4Byte i;
//Reload MacBB Parameters
for (i = 0; i < MAC_REG_NUM_8814; i++){
ODM_Write4Byte(pDM_Odm, Backup_MAC_REG[i], MAC_backup[i]);
}
for (i = 0; i < BB_REG_NUM_8814; i++){
ODM_Write4Byte(pDM_Odm, Backup_BB_REG[i], BB_backup[i]);
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreMacBB Success!!!!\n"));
}
VOID
Phydm_NHMCounterStatisticsInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
{
//PHY parameters initialize for ac series
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11AC+2, 0xC350); //0x990[31:16]=0xC350 Time duration for NHM unit: us, 0xc350=200ms
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC+2, 0xffff); //0x994[31:16]=0xffff th_9, th_10
//ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff5c); //0x998=0xffffff5c th_3, th_2, th_1, th_0
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff50); //0x998=0xffffff52 th_3, th_2, th_1, th_0
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff); //0x99c=0xffffffff th_7, th_6, th_5, th_4
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, 0xff); //0x9a0[7:0]=0xff th_8
//ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8|BIT9|BIT10, 0x7); //0x994[9:8]=3 enable CCX
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8|BIT9|BIT10, 0x1); //0x994[10:8]=1 ignoreCCA ignore PHYTXON enable CCX
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_9E8_11AC, BIT0, 0x1); //0x9e8[7]=1 max power among all RX ants
}
else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
{
//PHY parameters initialize for n series
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N+2, 0xC350); //0x894[31:16]=0x0xC350 Time duration for NHM unit: us, 0xc350=200ms
//ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N+2, 0x4e20); //0x894[31:16]=0x4e20 Time duration for NHM unit: 4us, 0x4e20=80ms
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N+2, 0xffff); //0x890[31:16]=0xffff th_9, th_10
//ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff5c); //0x898=0xffffff5c th_3, th_2, th_1, th_0
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff50); //0x898=0xffffff52 th_3, th_2, th_1, th_0
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff); //0x89c=0xffffffff th_7, th_6, th_5, th_4
ODM_SetBBReg(pDM_Odm, ODM_REG_FPGA0_IQK_11N, bMaskByte0, 0xff); //0xe28[7:0]=0xff th_8
//ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x7); //0x890[9:8]=3 enable CCX
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x1); //0x890[10:8]=1 ignoreCCA ignore PHYTXON enable CCX
ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT7, 0x1); //0xc0c[7]=1 max power among all RX ants
}
}
VOID
_IQK_AFESetting_8814A(
IN PDM_ODM_T pDM_Odm,
IN BOOLEAN Do_IQK
)
{
if(Do_IQK)
{
// IQK AFE Setting RX_WAIT_CCA mode
ODM_Write4Byte(pDM_Odm, 0xc60, 0x0e808003);
ODM_Write4Byte(pDM_Odm, 0xe60, 0x0e808003);
ODM_Write4Byte(pDM_Odm, 0x1860, 0x0e808003);
ODM_Write4Byte(pDM_Odm, 0x1a60, 0x0e808003);
ODM_SetBBReg(pDM_Odm, 0x90c, BIT(13), 0x1);
ODM_SetBBReg(pDM_Odm, 0x764, BIT(10)|BIT(9), 0x3);
ODM_SetBBReg(pDM_Odm, 0x764, BIT(10)|BIT(9), 0x0);
ODM_SetBBReg(pDM_Odm, 0x804, BIT(2), 0x1);
ODM_SetBBReg(pDM_Odm, 0x804, BIT(2), 0x0);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AFE IQK mode Success!!!!\n"));
}
else
{
ODM_Write4Byte(pDM_Odm, 0xc60, 0x07808003);
ODM_Write4Byte(pDM_Odm, 0xe60, 0x07808003);
ODM_Write4Byte(pDM_Odm, 0x1860, 0x07808003);
ODM_Write4Byte(pDM_Odm, 0x1a60, 0x07808003);
ODM_SetBBReg(pDM_Odm, 0x90c, BIT(13), 0x1);
ODM_SetBBReg(pDM_Odm, 0x764, BIT(10)|BIT(9), 0x3);
ODM_SetBBReg(pDM_Odm, 0x764, BIT(10)|BIT(9), 0x0);
ODM_SetBBReg(pDM_Odm, 0x804, BIT(2), 0x1);
ODM_SetBBReg(pDM_Odm, 0x804, BIT(2), 0x0);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AFE Normal mode Success!!!!\n"));
}
}
VOID
HalTxbf8192E_Enter(
IN PVOID pDM_VOID,
IN u1Byte BFerBFeeIdx
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u1Byte i = 0;
u1Byte BFerIdx = (BFerBFeeIdx & 0xF0) >> 4;
u1Byte BFeeIdx = (BFerBFeeIdx & 0xF);
u4Byte CSI_Param;
PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo;
RT_BEAMFORMEE_ENTRY BeamformeeEntry;
RT_BEAMFORMER_ENTRY BeamformerEntry;
u2Byte STAid = 0;
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
halTxbf8192E_RfMode(pDM_Odm, pBeamformingInfo);
if (pDM_Odm->RFType == ODM_2T2R)
ODM_Write4Byte(pDM_Odm, 0xd80, 0x00000000); /*Nc =2*/
if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) {
BeamformerEntry = pBeamformingInfo->BeamformerEntry[BFerIdx];
/*Sounding protocol control*/
ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8192E, 0xCB);
/*MAC address/Partial AID of Beamformer*/
if (BFerIdx == 0) {
for (i = 0; i < 6 ; i++)
ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8192E+i), BeamformerEntry.MacAddr[i]);
} else {
for (i = 0; i < 6 ; i++)
ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER1_INFO_8192E+i), BeamformerEntry.MacAddr[i]);
}
/*CSI report parameters of Beamformer Default use Nc = 2*/
CSI_Param = 0x03090309;
ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8192E, CSI_Param);
ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8192E, CSI_Param);
ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8192E, CSI_Param);
/*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us, MP chip)*/
ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8192E+3, 0x50);
}
if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) {
BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[BFeeIdx];
if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS))
STAid = BeamformeeEntry.MacId;
else
STAid = BeamformeeEntry.P_AID;
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s], STAid=0x%X\n", __func__, STAid));
/*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
if (BFeeIdx == 0) {
ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E, STAid);
ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8192E+3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8192E+3) | BIT4 | BIT6 | BIT7);
} else
ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E+2, STAid | BIT12 | BIT14 | BIT15);
/*CSI report parameters of Beamformee*/
if (BFeeIdx == 0) {
/*Get BIT24 & BIT25*/
u1Byte tmp = ODM_Read1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+3) & 0x3;
ODM_Write1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+3, tmp | 0x60);
ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E, STAid | BIT9);
} else {
/*Set BIT25*/
ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, STAid | 0xE200);
}
phydm_Beamforming_Notify(pDM_Odm);
}
}
VOID
PHY_ResetIQKResult_8814A(
IN PDM_ODM_T pDM_Odm
)
{
ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000000);
ODM_Write4Byte(pDM_Odm, 0x1b38, 0x20000000);
ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000002);
ODM_Write4Byte(pDM_Odm, 0x1b38, 0x20000000);
ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000004);
ODM_Write4Byte(pDM_Odm, 0x1b38, 0x20000000);
ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000006);
ODM_Write4Byte(pDM_Odm, 0x1b38, 0x20000000);
ODM_Write4Byte(pDM_Odm, 0xc10, 0x100);
ODM_Write4Byte(pDM_Odm, 0xe10, 0x100);
ODM_Write4Byte(pDM_Odm, 0x1810, 0x100);
ODM_Write4Byte(pDM_Odm, 0x1a10, 0x100);
}
VOID
HalTxbf8821B_Enter(
IN PVOID pDM_VOID,
IN u1Byte BFerBFeeIdx
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u1Byte i = 0;
u1Byte BFerIdx = (BFerBFeeIdx & 0xF0) >> 4;
u1Byte BFeeIdx = (BFerBFeeIdx & 0xF);
u4Byte CSI_Param;
PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo;
RT_BEAMFORMEE_ENTRY BeamformeeEntry;
RT_BEAMFORMER_ENTRY BeamformerEntry;
u2Byte STAid = 0;
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Start!\n", __func__));
halTxbf8821B_RfMode(pDM_Odm, pBeamformingInfo);
if (pDM_Odm->RFType == ODM_2T2R)
ODM_SetBBReg(pDM_Odm, ODM_REG_CSI_CONTENT_VALUE, bMaskDWord, 0x00000000); /*Nc =2*/
else
ODM_SetBBReg(pDM_Odm, ODM_REG_CSI_CONTENT_VALUE, bMaskDWord, 0x01081008); /*Nc =1*/
if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) {
BeamformerEntry = pBeamformingInfo->BeamformerEntry[BFerIdx];
/*Sounding protocol control*/
ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8821B, 0xCB);
/*MAC address/Partial AID of Beamformer*/
if (BFerIdx == 0) {
for (i = 0; i < 6 ; i++)
ODM_Write1Byte(pDM_Odm, (REG_BFMER0_INFO_8812A + i), BeamformerEntry.MacAddr[i]);
/*CSI report use legacy ofdm so don't need to fill P_AID. */
/*PlatformEFIOWrite2Byte(Adapter, REG_BFMER0_INFO_8821B+6, BeamformEntry.P_AID); */
} else {
for (i = 0; i < 6 ; i++)
ODM_Write1Byte(pDM_Odm, (REG_BFMER1_INFO_8812A + i), BeamformerEntry.MacAddr[i]);
/*CSI report use legacy ofdm so don't need to fill P_AID.*/
/*PlatformEFIOWrite2Byte(Adapter, REG_BFMER1_INFO_8821B+6, BeamformEntry.P_AID);*/
}
/*CSI report parameters of Beamformee*/
if (BeamformerEntry.BeamformEntryCap & BEAMFORMEE_CAP_VHT_SU) {
if (pDM_Odm->RFType == ODM_2T2R)
CSI_Param = 0x01090109;
else
CSI_Param = 0x01080108;
} else {
if (pDM_Odm->RFType == ODM_2T2R)
CSI_Param = 0x03090309;
else
CSI_Param = 0x03080308;
}
ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8821B, CSI_Param);
ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8821B, CSI_Param);
ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8821B, CSI_Param);
/*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us, MP chip)*/
ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8821B + 3, 0x50);
}
if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) {
BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[BFeeIdx];
if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS))
STAid = BeamformeeEntry.MacId;
else
STAid = BeamformeeEntry.P_AID;
/*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
if (BFeeIdx == 0) {
ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8821B, STAid);
ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8821B + 3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8821B + 3) | BIT4 | BIT6 | BIT7);
} else
ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8821B + 2, STAid | BIT12 | BIT14 | BIT15);
/*CSI report parameters of Beamformee*/
if (BFeeIdx == 0) {
/*Get BIT24 & BIT25*/
u1Byte tmp = ODM_Read1Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 3) & 0x3;
ODM_Write1Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 3, tmp | 0x60);
ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A, STAid | BIT9);
} else {
/*Set BIT25*/
ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 2, STAid | 0xE200);
}
phydm_Beamforming_Notify(pDM_Odm);
}
}
