void omap_writel(u32 v, u32 pa)
{
if (cpu_class_is_omap1())
__raw_writel(v, OMAP1_IO_ADDRESS(pa));
else
__raw_writel(v, OMAP2_IO_ADDRESS(pa));
}
u32 omap_readl(u32 pa)
{
if (cpu_class_is_omap1())
return __raw_readl(OMAP1_IO_ADDRESS(pa));
else
return __raw_readl(OMAP2_IO_ADDRESS(pa));
}
void omap_writew(u16 v, u32 pa)
{
if (cpu_class_is_omap1())
__raw_writew(v, OMAP1_IO_ADDRESS(pa));
else
__raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
}
/**
* omap1_get_reset_sources - return the source of the SoC's last reset
*
* Returns bits that represent the last reset source for the SoC. The
* format is standardized across OMAPs for use by the OMAP watchdog.
*/
u32 omap1_get_reset_sources(void)
{
u32 ret = 0;
u16 rs;
rs = __raw_readw(OMAP1_IO_ADDRESS(ARM_SYSST));
if (rs & (1 << ARM_SYSST_POR_SHIFT))
ret |= 1 << OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT;
if (rs & (1 << ARM_SYSST_EXT_RST_SHIFT))
ret |= 1 << OMAP_EXTWARM_RST_SRC_ID_SHIFT;
if (rs & (1 << ARM_SYSST_ARM_WDRST_SHIFT))
ret |= 1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT;
if (rs & (1 << ARM_SYSST_GLOB_SWRST_SHIFT))
ret |= 1 << OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT;
return ret;
}
#define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6 )
#define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7 )
#define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0 )
#define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1 )
extern struct nand_oobinfo jffs2_oobinfo;
/*
* MTD structure for OMAP board
*/
static struct mtd_info *omap_mtd;
static struct clk *omap_nand_clk;
static int omap_nand_dma_ch;
static struct completion omap_nand_dma_comp;
static unsigned long omap_nand_base = OMAP1_IO_ADDRESS(NAND_BASE);
static inline u32 nand_read_reg(int idx)
{
return __raw_readl(omap_nand_base + idx);
}
static inline void nand_write_reg(int idx, u32 val)
{
__raw_writel(val, omap_nand_base + idx);
}
static inline u8 nand_read_reg8(int idx)
{
return __raw_readb(omap_nand_base + idx);
}
void omap_writel(u32 v, u32 pa)
{
__raw_writel(v, OMAP1_IO_ADDRESS(pa));
}
void omap_writew(u16 v, u32 pa)
{
__raw_writew(v, OMAP1_IO_ADDRESS(pa));
}
void omap_writeb(u8 v, u32 pa)
{
__raw_writeb(v, OMAP1_IO_ADDRESS(pa));
}
u32 omap_readl(u32 pa)
{
return __raw_readl(OMAP1_IO_ADDRESS(pa));
}
u16 omap_readw(u32 pa)
{
return __raw_readw(OMAP1_IO_ADDRESS(pa));
}
u8 omap_readb(u32 pa)
{
return __raw_readb(OMAP1_IO_ADDRESS(pa));
}
.ops = &clkops_null,
.parent = &ck_ref,
};
/*
* FIXME: This clock seems to be necessary but no-one has asked for its
* activation. [ FIX: SoSSI, SSR ]
*/
static struct arm_idlect1_clk ck_dpll1out = {
.clk = {
.name = "ck_dpll1out",
.ops = &clkops_generic,
.parent = &ck_dpll1,
.flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT |
ENABLE_ON_INIT,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_CKOUT_ARM,
.recalc = &followparent_recalc,
},
.idlect_shift = IDL_CLKOUT_ARM_SHIFT,
};
static struct clk sossi_ck = {
.name = "ck_sossi",
.ops = &clkops_generic,
.parent = &ck_dpll1out.clk,
.flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
.enable_bit = CONF_MOD_SOSSI_CLK_EN_R,
.recalc = &omap1_sossi_recalc,
.set_rate = &omap1_set_sossi_rate,
static int cbus_transfer(struct cbus_host *host, int dev, int reg, int data)
{
int i;
int is_read = 0;
unsigned long flags;
u32 base;
#ifdef CONFIG_ARCH_OMAP1
base = OMAP1_IO_ADDRESS(OMAP1_MPUIO_BASE);
#else
base = 0;
#endif
if (data < 0)
is_read = 1;
/* We don't want interrupts disturbing our transfer */
spin_lock_irqsave(&host->lock, flags);
/* Reset state and start of transfer, SEL stays down during transfer */
cbus_set_gpio_dataout(base, host->sel_gpio, 0);
/* Set the DAT pin to output */
cbus_output(base, host->dat_gpio, 1);
/* Send the device address */
for (i = 3; i > 0; i--)
cbus_send_bit(host, base, dev & (1 << (i - 1)), 0);
/* Send the rw flag */
cbus_send_bit(host, base, is_read, 0);
/* Send the register address */
for (i = 5; i > 0; i--) {
int set_to_input = 0;
if (is_read && i == 1)
set_to_input = 1;
cbus_send_bit(host, base, reg & (1 << (i - 1)), set_to_input);
}
if (!is_read) {
for (i = 16; i > 0; i--)
cbus_send_bit(host, base, data & (1 << (i - 1)), 0);
} else {
cbus_set_gpio_dataout(base, host->clk_gpio, 1);
data = 0;
for (i = 16; i > 0; i--) {
u8 bit = cbus_receive_bit(host, base);
if (bit)
data |= 1 << (i - 1);
}
}
/* Indicate end of transfer, SEL goes up until next transfer */
cbus_set_gpio_dataout(base, host->sel_gpio, 1);
cbus_set_gpio_dataout(base, host->clk_gpio, 1);
cbus_set_gpio_dataout(base, host->clk_gpio, 0);
spin_unlock_irqrestore(&host->lock, flags);
return is_read ? data : 0;
}
*/
static void __init omap_serial_reset(struct plat_serial8250_port *p)
{
omap_serial_outp(p, UART_OMAP_MDR1, 0x07); /* disable UART */
omap_serial_outp(p, UART_OMAP_SCR, 0x08); /* TX watermark */
omap_serial_outp(p, UART_OMAP_MDR1, 0x00); /* enable UART */
if (!cpu_is_omap15xx()) {
omap_serial_outp(p, UART_OMAP_SYSC, 0x01);
while (!(omap_serial_in(p, UART_OMAP_SYSC) & 0x01));
}
}
static struct plat_serial8250_port serial_platform_data[] = {
{
.membase = OMAP1_IO_ADDRESS(OMAP_UART1_BASE),
.mapbase = OMAP_UART1_BASE,
.irq = INT_UART1,
.flags = UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = OMAP16XX_BASE_BAUD * 16,
},
{
.membase = OMAP1_IO_ADDRESS(OMAP_UART2_BASE),
.mapbase = OMAP_UART2_BASE,
.irq = INT_UART2,
.flags = UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = OMAP16XX_BASE_BAUD * 16,
