/* init_ops read/poll commands */ static void ecore_init_cmd_rd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, struct init_read_op *cmd) { bool (*comp_check)(u32 val, u32 expected_val); u32 delay = ECORE_INIT_POLL_PERIOD_US, val; u32 data, addr, poll; int i; data = OSAL_LE32_TO_CPU(cmd->op_data); addr = GET_FIELD(data, INIT_READ_OP_ADDRESS) << 2; poll = GET_FIELD(data, INIT_READ_OP_POLL_TYPE); #ifndef ASIC_ONLY if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) delay *= 100; #endif val = ecore_rd(p_hwfn, p_ptt, addr); if (poll == INIT_POLL_NONE) return; switch (poll) { case INIT_POLL_EQ: comp_check = comp_eq; break; case INIT_POLL_OR: comp_check = comp_or; break; case INIT_POLL_AND: comp_check = comp_and; break; default: DP_ERR(p_hwfn, "Invalid poll comparison type %08x\n", cmd->op_data); return; } data = OSAL_LE32_TO_CPU(cmd->expected_val); for (i = 0; i < ECORE_INIT_MAX_POLL_COUNT && !comp_check(val, data); i++) { OSAL_UDELAY(delay); val = ecore_rd(p_hwfn, p_ptt, addr); } if (i == ECORE_INIT_MAX_POLL_COUNT) DP_ERR(p_hwfn, "Timeout when polling reg: 0x%08x [ Waiting-for: %08x Got: %08x (comparison %08x)]\n", addr, OSAL_LE32_TO_CPU(cmd->expected_val), val, OSAL_LE32_TO_CPU(cmd->op_data)); }
static u32 ecore_init_cmd_phase(struct init_if_phase_op *p_cmd, u32 phase, u32 phase_id) { u32 data = OSAL_LE32_TO_CPU(p_cmd->phase_data); u32 op_data = OSAL_LE32_TO_CPU(p_cmd->op_data); if (!(GET_FIELD(data, INIT_IF_PHASE_OP_PHASE) == phase && (GET_FIELD(data, INIT_IF_PHASE_OP_PHASE_ID) == ANY_PHASE_ID || GET_FIELD(data, INIT_IF_PHASE_OP_PHASE_ID) == phase_id))) return GET_FIELD(op_data, INIT_IF_PHASE_OP_CMD_OFFSET); else return 0; }
/* init_ops write command */ static enum _ecore_status_t ecore_init_cmd_wr(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, struct init_write_op *p_cmd, bool b_can_dmae) { enum _ecore_status_t rc = ECORE_SUCCESS; bool b_must_dmae; u32 addr, data; data = OSAL_LE32_TO_CPU(p_cmd->data); b_must_dmae = GET_FIELD(data, INIT_WRITE_OP_WIDE_BUS); addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2; /* Sanitize */ if (b_must_dmae && !b_can_dmae) { DP_NOTICE(p_hwfn, true, "Need to write to %08x for Wide-bus but DMAE isn't" " allowed\n", addr); return ECORE_INVAL; } switch (GET_FIELD(data, INIT_WRITE_OP_SOURCE)) { case INIT_SRC_INLINE: data = OSAL_LE32_TO_CPU(p_cmd->args.inline_val); ecore_wr(p_hwfn, p_ptt, addr, data); break; case INIT_SRC_ZEROS: data = OSAL_LE32_TO_CPU(p_cmd->args.zeros_count); if (b_must_dmae || (b_can_dmae && (data >= 64))) rc = ecore_init_fill_dmae(p_hwfn, p_ptt, addr, 0, data); else ecore_init_fill(p_hwfn, p_ptt, addr, 0, data); break; case INIT_SRC_ARRAY: rc = ecore_init_cmd_array(p_hwfn, p_ptt, p_cmd, b_must_dmae, b_can_dmae); break; case INIT_SRC_RUNTIME: ecore_init_rt(p_hwfn, p_ptt, addr, OSAL_LE16_TO_CPU(p_cmd->args.runtime.offset), OSAL_LE16_TO_CPU(p_cmd->args.runtime.size), b_must_dmae); break; } return rc; }
static u32 ecore_init_cmd_mode(struct ecore_hwfn *p_hwfn, struct init_if_mode_op *p_cmd, int modes) { u16 offset = OSAL_LE16_TO_CPU(p_cmd->modes_buf_offset); if (ecore_init_cmd_mode_match(p_hwfn, &offset, modes)) return 0; else return GET_FIELD(OSAL_LE32_TO_CPU(p_cmd->op_data), INIT_IF_MODE_OP_CMD_OFFSET); }
enum _ecore_status_t ecore_init_run(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, int phase, int phase_id, int modes) { struct ecore_dev *p_dev = p_hwfn->p_dev; u32 cmd_num, num_init_ops; union init_op *init_ops; bool b_dmae = false; enum _ecore_status_t rc = ECORE_SUCCESS; num_init_ops = p_dev->fw_data->init_ops_size; init_ops = p_dev->fw_data->init_ops; #ifdef CONFIG_ECORE_ZIPPED_FW p_hwfn->unzip_buf = OSAL_ZALLOC(p_hwfn->p_dev, GFP_ATOMIC, MAX_ZIPPED_SIZE * 4); if (!p_hwfn->unzip_buf) { DP_NOTICE(p_hwfn, true, "Failed to allocate unzip buffer\n"); return ECORE_NOMEM; } #endif for (cmd_num = 0; cmd_num < num_init_ops; cmd_num++) { union init_op *cmd = &init_ops[cmd_num]; u32 data = OSAL_LE32_TO_CPU(cmd->raw.op_data); switch (GET_FIELD(data, INIT_CALLBACK_OP_OP)) { case INIT_OP_WRITE: rc = ecore_init_cmd_wr(p_hwfn, p_ptt, &cmd->write, b_dmae); break; case INIT_OP_READ: ecore_init_cmd_rd(p_hwfn, p_ptt, &cmd->read); break; case INIT_OP_IF_MODE: cmd_num += ecore_init_cmd_mode(p_hwfn, &cmd->if_mode, modes); break; case INIT_OP_IF_PHASE: cmd_num += ecore_init_cmd_phase(&cmd->if_phase, phase, phase_id); b_dmae = GET_FIELD(data, INIT_IF_PHASE_OP_DMAE_ENABLE); break; case INIT_OP_DELAY: /* ecore_init_run is always invoked from * sleep-able context */ OSAL_UDELAY(cmd->delay.delay); break; case INIT_OP_CALLBACK: rc = ecore_init_cmd_cb(p_hwfn, p_ptt, &cmd->callback); break; } if (rc) break; } #ifdef CONFIG_ECORE_ZIPPED_FW OSAL_FREE(p_hwfn->p_dev, p_hwfn->unzip_buf); p_hwfn->unzip_buf = OSAL_NULL; #endif return rc; }
static enum _ecore_status_t ecore_init_cmd_array(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, struct init_write_op *cmd, bool b_must_dmae, bool b_can_dmae) { u32 dmae_array_offset = OSAL_LE32_TO_CPU(cmd->args.array_offset); u32 data = OSAL_LE32_TO_CPU(cmd->data); u32 addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2; #ifdef CONFIG_ECORE_ZIPPED_FW u32 offset, output_len, input_len, max_size; #endif struct ecore_dev *p_dev = p_hwfn->p_dev; union init_array_hdr *hdr; const u32 *array_data; enum _ecore_status_t rc = ECORE_SUCCESS; u32 size; array_data = p_dev->fw_data->arr_data; hdr = (union init_array_hdr *) (array_data + dmae_array_offset); data = OSAL_LE32_TO_CPU(hdr->raw.data); switch (GET_FIELD(data, INIT_ARRAY_RAW_HDR_TYPE)) { case INIT_ARR_ZIPPED: #ifdef CONFIG_ECORE_ZIPPED_FW offset = dmae_array_offset + 1; input_len = GET_FIELD(data, INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE); max_size = MAX_ZIPPED_SIZE * 4; OSAL_MEMSET(p_hwfn->unzip_buf, 0, max_size); output_len = OSAL_UNZIP_DATA(p_hwfn, input_len, (u8 *)&array_data[offset], max_size, (u8 *)p_hwfn->unzip_buf); if (output_len) { rc = ecore_init_array_dmae(p_hwfn, p_ptt, addr, 0, output_len, p_hwfn->unzip_buf, b_must_dmae, b_can_dmae); } else { DP_NOTICE(p_hwfn, true, "Failed to unzip dmae data\n"); rc = ECORE_INVAL; } #else DP_NOTICE(p_hwfn, true, "Using zipped firmware without config enabled\n"); rc = ECORE_INVAL; #endif break; case INIT_ARR_PATTERN: { u32 repeats = GET_FIELD(data, INIT_ARRAY_PATTERN_HDR_REPETITIONS); u32 i; size = GET_FIELD(data, INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE); for (i = 0; i < repeats; i++, addr += size << 2) { rc = ecore_init_array_dmae(p_hwfn, p_ptt, addr, dmae_array_offset + 1, size, array_data, b_must_dmae, b_can_dmae); if (rc) break; } break; } case INIT_ARR_STANDARD: size = GET_FIELD(data, INIT_ARRAY_STANDARD_HDR_SIZE); rc = ecore_init_array_dmae(p_hwfn, p_ptt, addr, dmae_array_offset + 1, size, array_data, b_must_dmae, b_can_dmae); break; } return rc; }