void ar9300StopSpectralScan(struct ath_hal *ah) { u_int32_t val; struct ath_hal_9300 *ahp = AH9300(ah); val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN); // Deactivate spectral scan // HW Bug fix -- Do not disable the spectral scan // only turn off the active bit //val &= ~AR_PHY_SPECTRAL_SCAN_ENABLE; val &= ~AR_PHY_SPECTRAL_SCAN_ACTIVE; OS_REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val); val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN); OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_CF_BIN_THRESH, ahp->ah_radar1); OS_REG_RMW_FIELD(ah, AR_PHY_TIMING2, AR_PHY_TIMING2_DC_OFFSET, ahp->ah_dc_offset); OS_REG_WRITE(ah, AR_PHY_ERR, 0); if (AH_PRIVATE(ah)->ah_curchan && IS_5GHZ_FAST_CLOCK_EN(ah, AH_PRIVATE(ah)->ah_curchan)) { /* fast clock */ OS_REG_RMW_FIELD(ah, AR_PHY_MODE, AR_PHY_MODE_DISABLE_CCK, ahp->ah_disable_cck); } HDPRINTF(ah, HAL_DBG_UNMASKABLE, "%s: AR_PHY_MODE=0x%x\n", __func__, OS_REG_READ(ah, AR_PHY_MODE)); val = OS_REG_READ(ah, AR_PHY_ERR_MASK_REG) & (~AR_PHY_ERR_RADAR); OS_REG_WRITE(ah, AR_PHY_ERR_MASK_REG, val); val = OS_REG_READ(ah, AR_PHY_ERR); }
/* * Notify Power Mgt is enabled in self-generated frames. * If requested, force chip awake. * * Returns A_OK if chip is awake or successfully forced awake. * * WARNING WARNING WARNING * There is a problem with the chip where sometimes it will not wake up. */ static HAL_BOOL ar5211SetPowerModeAwake(struct ath_hal *ah, int setChip) { #define POWER_UP_TIME 2000 uint32_t val; int i; if (setChip) { OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_WAKE); OS_DELAY(10); /* Give chip the chance to awake */ for (i = POWER_UP_TIME / 200; i != 0; i--) { val = OS_REG_READ(ah, AR_PCICFG); if ((val & AR_PCICFG_SPWR_DN) == 0) break; OS_DELAY(200); OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_WAKE); } if (i == 0) { #ifdef AH_DEBUG ath_hal_printf(ah, "%s: Failed to wakeup in %ums\n", __func__, POWER_UP_TIME/20); #endif return AH_FALSE; } } OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); return AH_TRUE; #undef POWER_UP_TIME }
void ar9300StopSpectralScan(struct ath_hal *ah) { u_int32_t val; struct ath_hal_9300 *ahp = AH9300(ah); val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN); // Deactivate spectral scan val &= ~AR_PHY_SPECTRAL_SCAN_ENABLE; val &= ~AR_PHY_SPECTRAL_SCAN_ACTIVE; OS_REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val); val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN); OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_CF_BIN_THRESH, ahp->ah_radar1); OS_REG_RMW_FIELD(ah, AR_PHY_TIMING2, AR_PHY_TIMING2_DC_OFFSET, ahp->ah_dc_offset); OS_REG_WRITE(ah, AR_PHY_ERR, 0); if (AH_PRIVATE(ah)->ah_curchan && IS_5GHZ_FAST_CLOCK_EN(ah, AH_PRIVATE(ah)->ah_curchan)) { /* fast clock */ OS_REG_RMW_FIELD(ah, AR_PHY_MODE, AR_PHY_MODE_DISABLE_CCK, ahp->ah_disable_cck); } val = OS_REG_READ(ah, AR_PHY_ERR); }
void ar9300SetCcaThreshold(struct ath_hal *ah, u_int8_t thresh62) { OS_REG_RMW_FIELD(ah, AR_PHY_CCA_0, AR_PHY_CCA_THRESH62, thresh62); OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, thresh62); //OS_REG_RMW_FIELD(ah, AR_PHY_EXTCHN_PWRTHR1, AR_PHY_EXT_CCA0_THRESH62, thresh62); OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, AR_PHY_EXT_CCA_THRESH62, thresh62); }
void ar5416SetCcaThreshold(struct ath_hal *ah, u_int8_t thresh62) { if (AR_SREV_MERLIN_10_OR_LATER(ah)) { OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, thresh62); OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, thresh62); OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, AR_PHY_EXT_CCA_THRESH62, thresh62); } else { OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62, thresh62); OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, AR_PHY_EXT_CCA_THRESH62, thresh62); } }
/* * Update the h/w interrupt registers to reflect a tx q's configuration. */ static void setTxQInterrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi) { struct ath_hal_5211 *ahp = AH5211(ah); HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", __func__ , ahp->ah_txOkInterruptMask , ahp->ah_txErrInterruptMask , ahp->ah_txDescInterruptMask , ahp->ah_txEolInterruptMask , ahp->ah_txUrnInterruptMask ); OS_REG_WRITE(ah, AR_IMR_S0, SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK) | SM(ahp->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC) ); OS_REG_WRITE(ah, AR_IMR_S1, SM(ahp->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR) | SM(ahp->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL) ); OS_REG_RMW_FIELD(ah, AR_IMR_S2, AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask); }
/* * Setup HW to collect samples used for current cal */ static void ar5416SetupMeasurement(struct ath_hal *ah, HAL_CAL_LIST *currCal) { /* Start calibration w/ 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples */ OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, currCal->calData->calCountMax); /* Select calibration to run */ switch (currCal->calData->calType) { case IQ_MISMATCH_CAL: OS_REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); HALDEBUG(ah, HAL_DEBUG_PERCAL, "%s: start IQ Mismatch calibration\n", __func__); break; case ADC_GAIN_CAL: OS_REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); HALDEBUG(ah, HAL_DEBUG_PERCAL, "%s: start ADC Gain calibration\n", __func__); break; case ADC_DC_CAL: OS_REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); HALDEBUG(ah, HAL_DEBUG_PERCAL, "%s: start ADC DC calibration\n", __func__); break; case ADC_DC_INIT_CAL: OS_REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT); HALDEBUG(ah, HAL_DEBUG_PERCAL, "%s: start Init ADC DC calibration\n", __func__); break; } /* Kick-off cal */ OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, AR_PHY_TIMING_CTRL4_DO_CAL); }
/* * Notify Power Mgt is disabled in self-generated frames. * If requested, force chip to sleep. */ static void ar5210SetPowerModeSleep(struct ath_hal *ah, int setChip) { OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SV); if (setChip) OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_SLP); }
/* * Notify Power Management is enabled in self-generating * fames. If request, set power mode of chip to * auto/normal. Duration in units of 128us (1/8 TU). */ static void ar5211SetPowerModeNetworkSleep(struct ath_hal *ah, int setChip) { OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); if (setChip) OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_NORM); }
/* * Take the MHz channel value and set the Channel value * * ASSUMES: Writes enabled to analog bus * * Actual Expression, * * For 2GHz channel, * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) * (freq_ref = 40MHz) * * For 5GHz channel, * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10) * (freq_ref = 40MHz/(24>>amodeRefSel)) * * For 5GHz channels which are 5MHz spaced, * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) * (freq_ref = 40MHz) */ static HAL_BOOL ar9280SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan) { uint16_t bMode, fracMode, aModeRefSel = 0; uint32_t freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; CHAN_CENTERS centers; uint32_t refDivA = 24; OS_MARK(ah, AH_MARK_SETCHANNEL, chan->ic_freq); ar5416GetChannelCenters(ah, chan, ¢ers); freq = centers.synth_center; reg32 = OS_REG_READ(ah, AR_PHY_SYNTH_CONTROL); reg32 &= 0xc0000000; if (freq < 4800) { /* 2 GHz, fractional mode */ uint32_t txctl; bMode = 1; fracMode = 1; aModeRefSel = 0; channelSel = (freq * 0x10000)/15; txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL); if (freq == 2484) { /* Enable channel spreading for channel 14 */ OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, txctl | AR_PHY_CCK_TX_CTRL_JAPAN); } else { OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN); } } else { bMode = 0; fracMode = 0; if ((freq % 20) == 0) { aModeRefSel = 3; } else if ((freq % 10) == 0) { aModeRefSel = 2; } else { aModeRefSel = 0; /* Enable 2G (fractional) mode for channels which are 5MHz spaced */ fracMode = 1; refDivA = 1; channelSel = (freq * 0x8000)/15; /* RefDivA setting */ OS_REG_RMW_FIELD(ah, AR_AN_SYNTH9, AR_AN_SYNTH9_REFDIVA, refDivA); } if (!fracMode) { ndiv = (freq * (refDivA >> aModeRefSel))/60; channelSel = ndiv & 0x1ff; channelFrac = (ndiv & 0xfffffe00) * 2; channelSel = (channelSel << 17) | channelFrac; } }
void ar5416DisableWeakSignal(struct ath_hal *ah) { // set firpwr to max (signed) OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRPWR, 0x7f); OS_REG_CLR_BIT(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRPWR_SIGN_BIT); // set firstep to max OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRSTEP, 0x3f); // set relpwr to max (signed) OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_RELPWR, 0x1f); OS_REG_CLR_BIT(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_RELPWR_SIGN_BIT); // set relstep to max (signed) OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_RELSTEP, 0x1f); OS_REG_CLR_BIT(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT); // set firpwr_low to max (signed) OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_FIRPWR, 0x7f); OS_REG_CLR_BIT(ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_FIRPWR_SIGN_BIT); // set firstep_low to max OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_FIRSTEP, 0x3f); // set relstep_low to max (signed) OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_RELSTEP, 0x1f); OS_REG_CLR_BIT(ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_RELSTEP_SIGN_BIT); }
void ar9300_disable_weak_signal(struct ath_hal *ah) { /* set firpwr to max (signed) */ OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRPWR, 0x7f); OS_REG_CLR_BIT(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRPWR_SIGN_BIT); /* set firstep to max */ OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRSTEP, 0x3f); /* set relpwr to max (signed) */ OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_RELPWR, 0x1f); OS_REG_CLR_BIT(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_RELPWR_SIGN_BIT); /* set relstep to max (signed) */ OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_RELSTEP, 0x1f); OS_REG_CLR_BIT(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT); /* set firpwr_low to max (signed) */ OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_FIRPWR, 0x7f); OS_REG_CLR_BIT( ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_FIRPWR_SIGN_BIT); /* set firstep_low to max */ OS_REG_RMW_FIELD( ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, 0x3f); /* set relstep_low to max (signed) */ OS_REG_RMW_FIELD( ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_RELSTEP, 0x1f); OS_REG_CLR_BIT( ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_RELSTEP_SIGN_BIT); }
static void ar9300_setup_test_addac_mode(struct ath_hal *ah) { #if AH_BYTE_ORDER == AH_BIG_ENDIAN /* byteswap Rx/Tx buffer to ensure correct layout */ HDPRINTF(ah, HAL_DBG_RF_PARAM, "%s: big endian - set AR_CFG_SWTB/AR_CFG_SWRB\n", __func__); OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTB | AR_CFG_SWRB, 0); #else /* Rx/Tx buffer should not be byteswaped */ if (OS_REG_READ(ah, AR_CFG) & (AR_CFG_SWTB | AR_CFG_SWRB)) { HDPRINTF(ah, HAL_DBG_UNMASKABLE, "%s: **WARNING: little endian but AR_CFG_SWTB/AR_CFG_SWRB set!\n", __func__); } #endif OS_REG_WRITE(ah, AR_PHY_TEST, 0); OS_REG_WRITE(ah, AR_PHY_TEST_CTL_STATUS, 0); /* cf_bbb_obs_sel=4'b0001 */ OS_REG_RMW_FIELD(ah, AR_PHY_TEST, AR_PHY_TEST_BBB_OBS_SEL, 0x1); /* cf_rx_obs_sel=5'b00000, this is the 5th bit */ OS_REG_CLR_BIT(ah, AR_PHY_TEST, AR_PHY_TEST_RX_OBS_SEL_BIT5); /* cf_tx_obs_sel=3'b111 */ OS_REG_RMW_FIELD( ah, AR_PHY_TEST_CTL_STATUS, AR_PHY_TEST_CTL_TX_OBS_SEL, 0x7); /* cf_tx_obs_mux_sel=2'b11 */ OS_REG_RMW_FIELD( ah, AR_PHY_TEST_CTL_STATUS, AR_PHY_TEST_CTL_TX_OBS_MUX_SEL, 0x3); /* enable TSTADC */ OS_REG_SET_BIT(ah, AR_PHY_TEST_CTL_STATUS, AR_PHY_TEST_CTL_TSTDAC_EN); /* cf_rx_obs_sel=5'b00000, these are the first 4 bits */ OS_REG_RMW_FIELD( ah, AR_PHY_TEST_CTL_STATUS, AR_PHY_TEST_CTL_RX_OBS_SEL, 0x0); /* tstdac_out_sel=2'b01 */ OS_REG_RMW_FIELD(ah, AR_PHY_TEST, AR_PHY_TEST_CHAIN_SEL, 0x1); }
/* * XXX txPower here is likely not the target txPower in the traditional * XXX sense, but is set by a call to ar9280olcGetTxGainIndex(). * XXX Thus, be careful if you're trying to use this routine yourself. */ void ar9280olcGetPDADCs(struct ath_hal *ah, uint32_t initTxGain, int txPower, uint8_t *pPDADCValues) { uint32_t i; uint32_t offset; OS_REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3); OS_REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3); OS_REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7, AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain); offset = txPower; for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++) if (i < offset) pPDADCValues[i] = 0x0; else pPDADCValues[i] = 0xFF; }
void ar9300_stop_spectral_scan(struct ath_hal *ah) { u_int32_t val; struct ath_hal_9300 *ahp = AH9300(ah); bool asleep = ahp->ah_chip_full_sleep; if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) { ar9300_set_power_mode(ah, HAL_PM_AWAKE, true); } val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN); /* deactivate spectral scan */ /* HW Bug fix -- Do not disable the spectral scan * only turn off the active bit */ //val &= ~AR_PHY_SPECTRAL_SCAN_ENABLE; val &= ~AR_PHY_SPECTRAL_SCAN_ACTIVE; OS_REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val); val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN); OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_CF_BIN_THRESH, ahp->ah_radar1); OS_REG_RMW_FIELD(ah, AR_PHY_TIMING2, AR_PHY_TIMING2_DC_OFFSET, ahp->ah_dc_offset); OS_REG_WRITE(ah, AR_PHY_ERR, 0); if (AH_PRIVATE(ah)->ah_curchan && IS_5GHZ_FAST_CLOCK_EN(ah, AH_PRIVATE(ah)->ah_curchan)) { /* fast clock */ OS_REG_RMW_FIELD(ah, AR_PHY_MODE, AR_PHY_MODE_DISABLE_CCK, ahp->ah_disable_cck); } val = OS_REG_READ(ah, AR_PHY_ERR); val = OS_REG_READ(ah, AR_PHY_ERR_MASK_REG) & (~AR_PHY_ERR_RADAR); OS_REG_WRITE(ah, AR_PHY_ERR_MASK_REG, val); if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) { ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, true); } }
void ar9300_disable_strong_signal(struct ath_hal *ah) { u_int32_t val; val = OS_REG_READ(ah, AR_PHY_TIMING5); val |= AR_PHY_TIMING5_RSSI_THR1A_ENA; OS_REG_WRITE(ah, AR_PHY_TIMING5, val); OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5, AR_PHY_TIMING5_RSSI_THR1A, 0x7f); }
/* * Set the GPIO Interrupt */ void ar5416GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel) { uint32_t val; HALASSERT(gpio < AR_NUM_GPIO); /* XXX bounds check gpio */ val = MS(OS_REG_READ(ah, AR_GPIO_INTR_OUT), AR_GPIO_INTR_CTRL); if (ilevel) /* 0 == interrupt on pin high */ val &= ~AR_GPIO_BIT(gpio); else /* 1 == interrupt on pin low */ val |= AR_GPIO_BIT(gpio); OS_REG_RMW_FIELD(ah, AR_GPIO_INTR_OUT, AR_GPIO_INTR_CTRL, val); /* Change the interrupt mask. */ val = MS(OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE), AR_INTR_GPIO); val |= AR_GPIO_BIT(gpio); OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_GPIO, val); val = MS(OS_REG_READ(ah, AR_INTR_ASYNC_MASK), AR_INTR_GPIO); val |= AR_GPIO_BIT(gpio); OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_MASK, AR_INTR_GPIO, val); }
/* * Run temperature compensation calibration. * * The TX gain table is adjusted depending upon the difference * between the initial PDADC value and the currently read * average TX power sample value. This value is only valid if * frames have been transmitted, so currPDADC will be 0 if * no frames have yet been transmitted. */ void ar9287olcTemperatureCompensation(struct ath_hal *ah) { uint32_t rddata; int32_t delta, currPDADC, slope; rddata = OS_REG_READ(ah, AR_PHY_TX_PWRCTRL4); currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT); HALDEBUG(ah, HAL_DEBUG_PERCAL, "%s: initPDADC=%d, currPDADC=%d\n", __func__, AH5416(ah)->initPDADC, currPDADC); if (AH5416(ah)->initPDADC == 0 || currPDADC == 0) { /* * Zero value indicates that no frames have been transmitted * yet, can't do temperature compensation until frames are * transmitted. */ return; } else { int8_t val; (void) (ath_hal_eepromGet(ah, AR_EEP_TEMPSENSE_SLOPE, &val)); slope = val; if (slope == 0) { /* to avoid divide by zero case */ delta = 0; } else { delta = ((currPDADC - AH5416(ah)->initPDADC)*4) / slope; } OS_REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11, AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta); OS_REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11, AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta); HALDEBUG(ah, HAL_DEBUG_PERCAL, "%s: delta=%d\n", __func__, delta); } }
/* * Once configured for I/O - set output lines */ HAL_BOOL ar5416GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val) { uint32_t reg; HALASSERT(gpio < AR_NUM_GPIO); reg = MS(OS_REG_READ(ah, AR_GPIO_INTR_OUT), AR_GPIO_OUT_VAL); if (val & 1) reg |= AR_GPIO_BIT(gpio); else reg &= ~AR_GPIO_BIT(gpio); OS_REG_RMW_FIELD(ah, AR_GPIO_INTR_OUT, AR_GPIO_OUT_VAL, reg); return AH_TRUE; }
/* * Run temperature compensation calibration. * * The TX gain table is adjusted depending upon the difference * between the initial PDADC value and the currently read * average TX power sample value. This value is only valid if * frames have been transmitted, so currPDADC will be 0 if * no frames have yet been transmitted. */ void ar9280olcTemperatureCompensation(struct ath_hal *ah) { uint32_t rddata, i; int delta, currPDADC, regval; uint8_t hpwr_5g = 0; if (! ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) return; rddata = OS_REG_READ(ah, AR_PHY_TX_PWRCTRL4); currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT); HALDEBUG(ah, HAL_DEBUG_PERCAL, "%s: called: initPDADC=%d, currPDADC=%d\n", __func__, AH5416(ah)->initPDADC, currPDADC); if (AH5416(ah)->initPDADC == 0 || currPDADC == 0) return; (void) (ath_hal_eepromGet(ah, AR_EEP_DAC_HPWR_5G, &hpwr_5g)); if (hpwr_5g) delta = (currPDADC - AH5416(ah)->initPDADC + 4) / 8; else delta = (currPDADC - AH5416(ah)->initPDADC + 5) / 10; HALDEBUG(ah, HAL_DEBUG_PERCAL, "%s: delta=%d, PDADCdelta=%d\n", __func__, delta, AH9280(ah)->PDADCdelta); if (delta != AH9280(ah)->PDADCdelta) { AH9280(ah)->PDADCdelta = delta; for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) { regval = AH9280(ah)->originalGain[i] - delta; if (regval < 0) regval = 0; OS_REG_RMW_FIELD(ah, AR_PHY_TX_GAIN_TBL1 + i * 4, AR_PHY_TX_GAIN, regval); } } }
/* * Set the GPIO Interrupt */ void ar5416GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel) { uint32_t val, mask; HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins); if (ilevel == HAL_GPIO_INTR_DISABLE) { val = MS(OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE), AR_INTR_ASYNC_ENABLE_GPIO) &~ AR_GPIO_BIT(gpio); OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_ASYNC_ENABLE_GPIO, val); mask = MS(OS_REG_READ(ah, AR_INTR_ASYNC_MASK), AR_INTR_ASYNC_MASK_GPIO) &~ AR_GPIO_BIT(gpio); OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_MASK, AR_INTR_ASYNC_MASK_GPIO, mask); /* Clear synchronous GPIO interrupt registers and pending interrupt flag */ val = MS(OS_REG_READ(ah, AR_INTR_SYNC_ENABLE), AR_INTR_SYNC_ENABLE_GPIO) &~ AR_GPIO_BIT(gpio); OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_ENABLE_GPIO, val); mask = MS(OS_REG_READ(ah, AR_INTR_SYNC_MASK), AR_INTR_SYNC_MASK_GPIO) &~ AR_GPIO_BIT(gpio); OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_MASK, AR_INTR_SYNC_MASK_GPIO, mask); val = MS(OS_REG_READ(ah, AR_INTR_SYNC_CAUSE), AR_INTR_SYNC_ENABLE_GPIO) | AR_GPIO_BIT(gpio); OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_CAUSE, AR_INTR_SYNC_ENABLE_GPIO, val); } else { val = MS(OS_REG_READ(ah, AR_GPIO_INTR_POL), AR_GPIO_INTR_POL_VAL); if (ilevel == HAL_GPIO_INTR_HIGH) { /* 0 == interrupt on pin high */ val &= ~AR_GPIO_BIT(gpio); } else if (ilevel == HAL_GPIO_INTR_LOW) { /* 1 == interrupt on pin low */ val |= AR_GPIO_BIT(gpio); } OS_REG_RMW_FIELD(ah, AR_GPIO_INTR_POL, AR_GPIO_INTR_POL_VAL, val); /* Change the interrupt mask. */ val = MS(OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE), AR_INTR_ASYNC_ENABLE_GPIO) | AR_GPIO_BIT(gpio); OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_ASYNC_ENABLE_GPIO, val); mask = MS(OS_REG_READ(ah, AR_INTR_ASYNC_MASK), AR_INTR_ASYNC_MASK_GPIO) | AR_GPIO_BIT(gpio); OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_MASK, AR_INTR_ASYNC_MASK_GPIO, mask); /* Set synchronous GPIO interrupt registers as well */ val = MS(OS_REG_READ(ah, AR_INTR_SYNC_ENABLE), AR_INTR_SYNC_ENABLE_GPIO) | AR_GPIO_BIT(gpio); OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_ENABLE_GPIO, val); mask = MS(OS_REG_READ(ah, AR_INTR_SYNC_MASK), AR_INTR_SYNC_MASK_GPIO) | AR_GPIO_BIT(gpio); OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_MASK, AR_INTR_SYNC_MASK_GPIO, mask); } AH5416(ah)->ah_gpioMask = mask; /* for ar5416SetInterrupts */ }
/* * Control Adaptive Noise Immunity Parameters */ HAL_BOOL ar5416AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param, HAL_BOOL inISR) { #define N(a) (sizeof(a)/sizeof(a[0])) typedef int TABLE[]; struct ath_hal_5416 *ahp = AH5416(ah); struct ar5416AniState *aniState = ahp->ah_curani; switch (cmd & ahp->ah_ani_function) { case HAL_ANI_NOISE_IMMUNITY_LEVEL: { u_int level = param; if (level >= N(ahp->ah_totalSizeDesired)) { HDPRINTF(ah, HAL_DBG_ANI, "%s: level out of range (%u > %u)\n", __func__, level, (unsigned) N(ahp->ah_totalSizeDesired)); return AH_FALSE; } OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_TOT_DES, ahp->ah_totalSizeDesired[level]); OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, AR_PHY_AGC_CTL1_COARSE_LOW, ahp->ah_coarseLow[level]); OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, AR_PHY_AGC_CTL1_COARSE_HIGH, ahp->ah_coarseHigh[level]); OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRPWR, ahp->ah_firpwr[level]); if (level > aniState->noiseImmunityLevel) ahp->ah_stats.ast_ani_niup++; else if (level < aniState->noiseImmunityLevel) ahp->ah_stats.ast_ani_nidown++; aniState->noiseImmunityLevel = level; break; } case HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION: { const TABLE m1ThreshLow = { 127, 50 }; const TABLE m2ThreshLow = { 127, 40 }; const TABLE m1Thresh = { 127, 0x4d }; const TABLE m2Thresh = { 127, 0x40 }; const TABLE m2CountThr = { 31, 16 }; const TABLE m2CountThrLow = { 63, 48 }; u_int on = param ? 1 : 0; OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, m1ThreshLow[on]); OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, m2ThreshLow[on]); OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, AR_PHY_SFCORR_M1_THRESH, m1Thresh[on]); OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, AR_PHY_SFCORR_M2_THRESH, m2Thresh[on]); OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, AR_PHY_SFCORR_M2COUNT_THR, m2CountThr[on]); OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2CountThrLow[on]); OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLow[on]); OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLow[on]); OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_M1_THRESH, m1Thresh[on]); OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_M2_THRESH, m2Thresh[on]); if (on) { OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); } else { OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); } if (!on != aniState->ofdmWeakSigDetectOff) { if (on) ahp->ah_stats.ast_ani_ofdmon++; else ahp->ah_stats.ast_ani_ofdmoff++; aniState->ofdmWeakSigDetectOff = !on; } break; } case HAL_ANI_CCK_WEAK_SIGNAL_THR: { const TABLE weakSigThrCck = { 8, 6 }; u_int high = param ? 1 : 0; OS_REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, weakSigThrCck[high]); if (high != aniState->cckWeakSigThreshold) { if (high) ahp->ah_stats.ast_ani_cckhigh++; else ahp->ah_stats.ast_ani_ccklow++; aniState->cckWeakSigThreshold = high; } break; } case HAL_ANI_FIRSTEP_LEVEL: { const TABLE firstep = { 0, 4, 8 }; u_int level = param; if (level >= N(firstep)) { HDPRINTF(ah, HAL_DBG_ANI, "%s: level out of range (%u > %u)\n", __func__, level, (unsigned) N(firstep)); return AH_FALSE; } OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRSTEP, firstep[level]); if (level > aniState->firstepLevel) ahp->ah_stats.ast_ani_stepup++; else if (level < aniState->firstepLevel) ahp->ah_stats.ast_ani_stepdown++; aniState->firstepLevel = level; break; } case HAL_ANI_SPUR_IMMUNITY_LEVEL: { const TABLE cycpwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }; u_int level = param; if (level >= N(cycpwrThr1)) { HDPRINTF(ah, HAL_DBG_ANI, "%s: level out of range (%u > %u)\n", __func__, level, (unsigned) N(cycpwrThr1)); return AH_FALSE; } OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5, AR_PHY_TIMING5_CYCPWR_THR1, cycpwrThr1[level]); if (level > aniState->spurImmunityLevel) ahp->ah_stats.ast_ani_spurup++; else if (level < aniState->spurImmunityLevel) ahp->ah_stats.ast_ani_spurdown++; aniState->spurImmunityLevel = level; break; } case HAL_ANI_PRESENT: break; #ifdef AH_PRIVATE_DIAG case HAL_ANI_MODE: if (param == 0) { ahp->ah_procPhyErr &= ~HAL_PROCESS_ANI; /* Turn off HW counters if we have them */ ar5416AniDetach(ah); ar5416SetRxFilter(ah, ar5416GetRxFilter(ah) &~ HAL_RX_FILTER_PHYERR); } else { /* normal/auto mode */ ahp->ah_procPhyErr |= HAL_PROCESS_ANI; if (ahp->ah_hasHwPhyCounters) { ar5416SetRxFilter(ah, ar5416GetRxFilter(ah) &~ HAL_RX_FILTER_PHYERR); } else { ar5416SetRxFilter(ah, ar5416GetRxFilter(ah) | HAL_RX_FILTER_PHYERR); } } break; case HAL_ANI_PHYERR_RESET: ahp->ah_stats.ast_ani_ofdmerrs = 0; ahp->ah_stats.ast_ani_cckerrs = 0; break; #endif /* AH_PRIVATE_DIAG */ default: HDPRINTF(ah, HAL_DBG_ANI, "%s: invalid cmd %u\n", __func__, cmd); return AH_FALSE; } HDPRINTF(ah, HAL_DBG_ANI, "%s: ANI parameters:\n", __func__); HDPRINTF(ah, HAL_DBG_ANI, "noiseImmunityLevel=%d, spurImmunityLevel=%d, ofdmWeakSigDetectOff=%d\n", aniState->noiseImmunityLevel, aniState->spurImmunityLevel, !aniState->ofdmWeakSigDetectOff); HDPRINTF(ah, HAL_DBG_ANI, "cckWeakSigThreshold=%d, firstepLevel=%d, listenTime=%d\n", aniState->cckWeakSigThreshold, aniState->firstepLevel, aniState->listenTime); HDPRINTF(ah, HAL_DBG_ANI, "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n", aniState->cycleCount, aniState->ofdmPhyErrCount, aniState->cckPhyErrCount); #ifndef REMOVE_PKT_LOG /* do pktlog */ { struct log_ani log_data; /* Populate the ani log record */ log_data.phyStatsDisable = DO_ANI(ah); log_data.noiseImmunLvl = aniState->noiseImmunityLevel; log_data.spurImmunLvl = aniState->spurImmunityLevel; log_data.ofdmWeakDet = aniState->ofdmWeakSigDetectOff; log_data.ofdmWeakDet = aniState->ofdmWeakSigDetectOff; log_data.cckWeakThr = aniState->cckWeakSigThreshold; log_data.firLvl = aniState->firstepLevel; log_data.listenTime = aniState->listenTime; log_data.cycleCount = aniState->cycleCount; log_data.ofdmPhyErrCount = aniState->ofdmPhyErrCount; log_data.cckPhyErrCount = aniState->cckPhyErrCount; log_data.rssi = 0; /* Was for legacy single antenna rssi */ /* For HT chips, 2x2 */ /* Log 6 u_int16_t RSSIs as first in the int32_t 'misc' array */ /* ToDo: Update pktRssi for valid packets? */ /* ToDo: Update PhyErr RSSIs in aniState variable - need Rx Descriptor / PhyErr*/ /* ToDo: Add parsing support in owldump, if needed */ log_data.misc[0] = aniState->pktRssi[0]; log_data.misc[1] = aniState->pktRssi[1]; log_data.misc[2] = aniState->ofdmErrRssi[0]; log_data.misc[3] = aniState->ofdmErrRssi[1]; log_data.misc[4] = aniState->cckErrRssi[0]; log_data.misc[5] = aniState->cckErrRssi[1]; if (inISR) ath_hal_log_ani(ah->ah_sc, &log_data, 1); // set interrupt context flag else ath_hal_log_ani(ah->ah_sc, &log_data, 0); // clear interrupt context flag } #endif return AH_TRUE; #undef N }
static HAL_BOOL ar2316SetPowerTable(struct ath_hal *ah, int16_t *minPower, int16_t *maxPower, const struct ieee80211_channel *chan, uint16_t *rfXpdGain) { struct ath_hal_5212 *ahp = AH5212(ah); const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; const RAW_DATA_STRUCT_2316 *pRawDataset = AH_NULL; uint16_t pdGainOverlap_t2; int16_t minCalPower2316_t2; uint16_t *pdadcValues = ahp->ah_pcdacTable; uint16_t gainBoundaries[4]; uint32_t reg32, regoffset; int i, numPdGainsUsed; #ifndef AH_USE_INIPDGAIN uint32_t tpcrg1; #endif HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan 0x%x flag 0x%x\n", __func__, chan->ic_freq, chan->ic_flags); if (IEEE80211_IS_CHAN_G(chan) || IEEE80211_IS_CHAN_108G(chan)) pRawDataset = &ee->ee_rawDataset2413[headerInfo11G]; else if (IEEE80211_IS_CHAN_B(chan)) pRawDataset = &ee->ee_rawDataset2413[headerInfo11B]; else { HALDEBUG(ah, HAL_DEBUG_ANY, "%s: illegal mode\n", __func__); return AH_FALSE; } pdGainOverlap_t2 = (uint16_t) SM(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP); numPdGainsUsed = ar2316getGainBoundariesAndPdadcsForPowers(ah, chan->channel, pRawDataset, pdGainOverlap_t2, &minCalPower2316_t2,gainBoundaries, rfXpdGain, pdadcValues); HALASSERT(1 <= numPdGainsUsed && numPdGainsUsed <= 3); #ifdef AH_USE_INIPDGAIN /* * Use pd_gains curve from eeprom; Atheros always uses * the default curve from the ini file but some vendors * (e.g. Zcomax) want to override this curve and not * honoring their settings results in tx power 5dBm low. */ OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, (pRawDataset->pDataPerChannel[0].numPdGains - 1)); #else tpcrg1 = OS_REG_READ(ah, AR_PHY_TPCRG1); tpcrg1 = (tpcrg1 &~ AR_PHY_TPCRG1_NUM_PD_GAIN) | SM(numPdGainsUsed-1, AR_PHY_TPCRG1_NUM_PD_GAIN); switch (numPdGainsUsed) { case 3: tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING3; tpcrg1 |= SM(rfXpdGain[2], AR_PHY_TPCRG1_PDGAIN_SETTING3); /* fall thru... */ case 2: tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING2; tpcrg1 |= SM(rfXpdGain[1], AR_PHY_TPCRG1_PDGAIN_SETTING2); /* fall thru... */ case 1: tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING1; tpcrg1 |= SM(rfXpdGain[0], AR_PHY_TPCRG1_PDGAIN_SETTING1); break; } #ifdef AH_DEBUG if (tpcrg1 != OS_REG_READ(ah, AR_PHY_TPCRG1)) HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: using non-default " "pd_gains (default 0x%x, calculated 0x%x)\n", __func__, OS_REG_READ(ah, AR_PHY_TPCRG1), tpcrg1); #endif OS_REG_WRITE(ah, AR_PHY_TPCRG1, tpcrg1); #endif /* * Note the pdadc table may not start at 0 dBm power, could be * negative or greater than 0. Need to offset the power * values by the amount of minPower for griffin */ if (minCalPower2316_t2 != 0) ahp->ah_txPowerIndexOffset = (int16_t)(0 - minCalPower2316_t2); else ahp->ah_txPowerIndexOffset = 0; /* Finally, write the power values into the baseband power table */ regoffset = 0x9800 + (672 <<2); /* beginning of pdadc table in griffin */ for (i = 0; i < 32; i++) { reg32 = ((pdadcValues[4*i + 0] & 0xFF) << 0) | ((pdadcValues[4*i + 1] & 0xFF) << 8) | ((pdadcValues[4*i + 2] & 0xFF) << 16) | ((pdadcValues[4*i + 3] & 0xFF) << 24) ; OS_REG_WRITE(ah, regoffset, reg32); regoffset += 4; } OS_REG_WRITE(ah, AR_PHY_TPCRG5, SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) | SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) | SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) | SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); return AH_TRUE; }
/* * Control Adaptive Noise Immunity Parameters */ HAL_BOOL ar5416AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param) { typedef int TABLE[]; struct ath_hal_5212 *ahp = AH5212(ah); struct ar5212AniState *aniState = ahp->ah_curani; const struct ar5212AniParams *params = aniState->params; OS_MARK(ah, AH_MARK_ANI_CONTROL, cmd); switch (cmd) { case HAL_ANI_NOISE_IMMUNITY_LEVEL: { u_int level = param; if (level >= params->maxNoiseImmunityLevel) { HALDEBUG(ah, HAL_DEBUG_ANY, "%s: immunity level out of range (%u > %u)\n", __func__, level, params->maxNoiseImmunityLevel); return AH_FALSE; } OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_TOT_DES, params->totalSizeDesired[level]); OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, AR_PHY_AGC_CTL1_COARSE_LOW, params->coarseLow[level]); OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, AR_PHY_AGC_CTL1_COARSE_HIGH, params->coarseHigh[level]); OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRPWR, params->firpwr[level]); if (level > aniState->noiseImmunityLevel) ahp->ah_stats.ast_ani_niup++; else if (level < aniState->noiseImmunityLevel) ahp->ah_stats.ast_ani_nidown++; aniState->noiseImmunityLevel = level; break; } case HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION: { static const TABLE m1ThreshLow = { 127, 50 }; static const TABLE m2ThreshLow = { 127, 40 }; static const TABLE m1Thresh = { 127, 0x4d }; static const TABLE m2Thresh = { 127, 0x40 }; static const TABLE m2CountThr = { 31, 16 }; static const TABLE m2CountThrLow = { 63, 48 }; u_int on = param ? 1 : 0; OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, m1ThreshLow[on]); OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, m2ThreshLow[on]); OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, AR_PHY_SFCORR_M1_THRESH, m1Thresh[on]); OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, AR_PHY_SFCORR_M2_THRESH, m2Thresh[on]); OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, AR_PHY_SFCORR_M2COUNT_THR, m2CountThr[on]); OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2CountThrLow[on]); OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLow[on]); OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLow[on]); OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_M1_THRESH, m1Thresh[on]); OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_M2_THRESH, m2Thresh[on]); if (on) { OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); } else { OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); } if (on) ahp->ah_stats.ast_ani_ofdmon++; else ahp->ah_stats.ast_ani_ofdmoff++; aniState->ofdmWeakSigDetectOff = !on; break; } case HAL_ANI_CCK_WEAK_SIGNAL_THR: { static const TABLE weakSigThrCck = { 8, 6 }; u_int high = param ? 1 : 0; OS_REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, weakSigThrCck[high]); if (high) ahp->ah_stats.ast_ani_cckhigh++; else ahp->ah_stats.ast_ani_ccklow++; aniState->cckWeakSigThreshold = high; break; } case HAL_ANI_FIRSTEP_LEVEL: { u_int level = param; if (level >= params->maxFirstepLevel) { HALDEBUG(ah, HAL_DEBUG_ANY, "%s: firstep level out of range (%u > %u)\n", __func__, level, params->maxFirstepLevel); return AH_FALSE; } OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRSTEP, params->firstep[level]); if (level > aniState->firstepLevel) ahp->ah_stats.ast_ani_stepup++; else if (level < aniState->firstepLevel) ahp->ah_stats.ast_ani_stepdown++; aniState->firstepLevel = level; break; } case HAL_ANI_SPUR_IMMUNITY_LEVEL: { u_int level = param; if (level >= params->maxSpurImmunityLevel) { HALDEBUG(ah, HAL_DEBUG_ANY, "%s: spur immunity level out of range (%u > %u)\n", __func__, level, params->maxSpurImmunityLevel); return AH_FALSE; } OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5, AR_PHY_TIMING5_CYCPWR_THR1, params->cycPwrThr1[level]); if (level > aniState->spurImmunityLevel) ahp->ah_stats.ast_ani_spurup++; else if (level < aniState->spurImmunityLevel) ahp->ah_stats.ast_ani_spurdown++; aniState->spurImmunityLevel = level; break; } case HAL_ANI_PRESENT: break; case HAL_ANI_MODE: if (param == 0) { ahp->ah_procPhyErr &= ~HAL_ANI_ENA; /* Turn off HW counters if we have them */ ar5416AniDetach(ah); ar5212SetRxFilter(ah, ar5212GetRxFilter(ah) &~ HAL_RX_FILTER_PHYERR); } else { /* normal/auto mode */ /* don't mess with state if already enabled */ if (ahp->ah_procPhyErr & HAL_ANI_ENA) break; ar5212SetRxFilter(ah, ar5212GetRxFilter(ah) &~ HAL_RX_FILTER_PHYERR); /* Enable MIB Counters */ enableAniMIBCounters(ah, ahp->ah_curani != AH_NULL ? ahp->ah_curani->params: &ahp->ah_aniParams24 /*XXX*/); ahp->ah_procPhyErr |= HAL_ANI_ENA; } break; #ifdef AH_PRIVATE_DIAG case HAL_ANI_PHYERR_RESET: ahp->ah_stats.ast_ani_ofdmerrs = 0; ahp->ah_stats.ast_ani_cckerrs = 0; break; #endif /* AH_PRIVATE_DIAG */ default: HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid cmd %u\n", __func__, cmd); return AH_FALSE; } return AH_TRUE; }
HAL_BOOL ar5416WowEnable(struct ath_hal *ah, u_int32_t pattern_enable, u_int32_t timeoutInSeconds, int clearbssid) { uint32_t init_val, val, rval=0; const int ka_delay = 4; /* Delay of 4 millisec between two KeepAlive's */ uint32_t wow_event_mask; /* * ah_wow_event_mask is a mask to the AR_WOW_PATTERN_REG register to indicate * which WOW events that we have enabled. The WOW Events are from the * pattern_enable in this function and pattern_count of ar5416WowApplyPattern() */ wow_event_mask = AH_PRIVATE(ah)->ah_wow_event_mask; /* * Untie Power-On-Reset from the PCI-E Reset. When we are in WOW sleep, * we do not want the Reset from the PCI-E to disturb our hw state. */ if (AR_SREV_MERLIN_20_OR_LATER(ah) && (AH_PRIVATE(ah)->ah_is_pci_express == AH_TRUE)) { /* * We need to untie the internal POR (power-on-reset) to the external * PCI-E reset. We also need to tie the PCI-E Phy reset to the PCI-E reset. */ u_int32_t wa_reg_val; if (AR_SREV_KITE(ah) || AR_SREV_KIWI(ah)) wa_reg_val = AR9285_WA_DEFAULT; else wa_reg_val = AR9280_WA_DEFAULT; /* * In Merlin and Kite, bit 14 in WA register (disable L1) should only * be set when device enters D3 and be cleared when device comes back to D0. */ if (AH_PRIVATE(ah)->ah_config.ath_hal_pcie_waen & AR_WA_D3_L1_DISABLE) wa_reg_val = wa_reg_val | AR_WA_D3_L1_DISABLE; wa_reg_val = wa_reg_val & ~(AR_WA_UNTIE_RESET_EN); wa_reg_val = wa_reg_val | AR_WA_RESET_EN | AR_WA_POR_SHORT; OS_REG_WRITE(ah, AR_WA, wa_reg_val); if (!AR_SREV_KITE(ah) || AR_SREV_KITE_12_OR_LATER(ah)) { /* s * For WOW sleep, we reprogram the SerDes so that the PLL and CHK REQ * are both enabled. This uses more power but the Maverick team reported * that otherwise, WOW sleep is unable and chip may disappears. */ ar928xConfigSerDes_WowSleep(ah); } } /* * Set the power states appropriately and enable pme. */ val = OS_REG_READ(ah, AR_PCIE_PM_CTRL); val |= AR_PMCTRL_HOST_PME_EN | \ AR_PMCTRL_PWR_PM_CTRL_ENA | AR_PMCTRL_AUX_PWR_DET; val &= ~AR_PMCTRL_WOW_PME_CLR; OS_REG_WRITE(ah, AR_PCIE_PM_CTRL, val); /* * Setup for for: * - beacon misses * - magic pattern * - keep alive timeout * - pattern matching */ /* * Program some default values for keep-alives, beacon misses, etc. */ init_val = OS_REG_READ(ah, AR_WOW_PATTERN_REG); val = AR_WOW_BACK_OFF_SHIFT(AR_WOW_PAT_BACKOFF) | init_val; OS_REG_WRITE(ah, AR_WOW_PATTERN_REG, val); rval = OS_REG_READ(ah, AR_WOW_PATTERN_REG); init_val = OS_REG_READ(ah, AR_WOW_COUNT_REG); val = AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT) | \ AR_WOW_SLOT_CNT(AR_WOW_CNT_SLOT_CNT) | \ AR_WOW_KEEP_ALIVE_CNT(AR_WOW_CNT_KA_CNT); OS_REG_WRITE(ah, AR_WOW_COUNT_REG, val); rval = OS_REG_READ(ah, AR_WOW_COUNT_REG); init_val = OS_REG_READ(ah, AR_WOW_BCN_TIMO_REG); if (pattern_enable & AH_WOW_BEACON_MISS) { val = AR_WOW_BEACON_TIMO; } else { /* We are not using the beacon miss. Program a large value. */ val = AR_WOW_BEACON_TIMO_MAX; } OS_REG_WRITE(ah, AR_WOW_BCN_TIMO_REG, val); rval = OS_REG_READ(ah, AR_WOW_BCN_TIMO_REG); init_val = OS_REG_READ(ah, AR_WOW_KEEP_ALIVE_TIMO_REG); /* * Keep Alive Timo in ms, except Merlin - see EV 62708 */ if (pattern_enable == 0 || AR_SREV_MERLIN(ah)) { val = AR_WOW_KEEP_ALIVE_NEVER; } else { val = AH_PRIVATE(ah)->ah_config.ath_hal_keep_alive_timeout * 32; } OS_REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO_REG, val); rval = OS_REG_READ(ah, AR_WOW_KEEP_ALIVE_TIMO_REG); init_val = OS_REG_READ(ah, AR_WOW_KEEP_ALIVE_DELAY_REG); /* * Keep Alive delay in us. Based on 'power on clock' , therefore in uSec */ val = ka_delay * 1000; OS_REG_WRITE(ah, AR_WOW_KEEP_ALIVE_DELAY_REG, val); rval = OS_REG_READ(ah, AR_WOW_KEEP_ALIVE_DELAY_REG); /* * Create KeepAlive Pattern to respond to beacons. */ ar5416WowCreateKeepAlivePattern(ah); /* * Configure Mac Wow Registers. */ val = OS_REG_READ(ah, AR_WOW_KEEP_ALIVE_REG); /* * Send keep alive timeouts anyway. */ val &= ~AR_WOW_KEEP_ALIVE_AUTO_DIS; if (pattern_enable & AH_WOW_LINK_CHANGE) { val &= ~ AR_WOW_KEEP_ALIVE_FAIL_DIS; wow_event_mask |= AR_WOW_KEEP_ALIVE_FAIL; } else { val |= AR_WOW_KEEP_ALIVE_FAIL_DIS; } OS_REG_WRITE(ah, AR_WOW_KEEP_ALIVE_REG, val); val = OS_REG_READ(ah, AR_WOW_KEEP_ALIVE_REG); val = OS_REG_READ(ah, AR_WOW_BCN_EN_REG); /* * We are relying on a bmiss failure. Ensure we have enough * threshold to prevent false positives. */ OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR, AR_WOW_BMISSTHRESHOLD); /* * Beacon miss & user pattern events are broken in Owl. * Enable only for Merlin. * The workaround is done at the ath_dev layer using the * sc->sc_wow_bmiss_intr field. * XXX: we need to cleanup this workaround before the next chip that * fixes this issue. */ if (!AR_SREV_MERLIN_10_OR_LATER(ah)) pattern_enable &= ~AH_WOW_BEACON_MISS; if (pattern_enable & AH_WOW_BEACON_MISS) { val |= AR_WOW_BEACON_FAIL_EN; wow_event_mask |= AR_WOW_BEACON_FAIL; } else { val &= ~AR_WOW_BEACON_FAIL_EN; } OS_REG_WRITE(ah, AR_WOW_BCN_EN_REG, val); val = OS_REG_READ(ah, AR_WOW_BCN_EN_REG); /* * Enable the magic packet registers. */ val = OS_REG_READ(ah, AR_WOW_PATTERN_REG); if (pattern_enable & AH_WOW_MAGIC_PATTERN_EN) { val |= AR_WOW_MAGIC_EN; wow_event_mask |= AR_WOW_MAGIC_PAT_FOUND; } else { val &= ~AR_WOW_MAGIC_EN; } val |= AR_WOW_MAC_INTR_EN; OS_REG_WRITE(ah, AR_WOW_PATTERN_REG, val); val = OS_REG_READ(ah, AR_WOW_PATTERN_REG); /* For Kite and later version of the chips * enable wow pattern match for packets less than * 256 bytes for all patterns. */ if (AR_SREV_KITE_10_OR_LATER(ah)) { OS_REG_WRITE(ah, AR_WOW_PATTERN_MATCH_LT_256B_REG, AR_WOW_PATTERN_SUPPORTED); } /* * Set the power states appropriately and enable pme. */ val = OS_REG_READ(ah, AR_PCIE_PM_CTRL); val |= AR_PMCTRL_PWR_STATE_D1D3 | AR_PMCTRL_HOST_PME_EN | AR_PMCTRL_PWR_PM_CTRL_ENA; OS_REG_WRITE(ah, AR_PCIE_PM_CTRL, val); if (timeoutInSeconds) { /* The clearbssid parameter is set only for the case where the wake needs to be on a timeout. The timeout mechanism, at this time, is specific to Maverick. For a manuf test, the system is put into sleep with a timer. On timer expiry, the chip interrupts(timer) and wakes the system. Clearbssid is specified as TRUE since we do not want a spurious beacon miss. If specified as true, we clear the bssid regs. */ // Setup the timer. OS_REG_WRITE(ah, AR_NEXT_NDP_TIMER, OS_REG_READ(ah, AR_TSF_L32) + timeoutInSeconds * 1000000 ); // convert Timeout to uSecs. OS_REG_WRITE(ah, AR_NDP_PERIOD, 30 * 1000000); // timer_period = 30 seconds always. OS_REG_WRITE(ah, AR_TIMER_MODE, OS_REG_READ(ah, AR_TIMER_MODE) | AR_NDP_TIMER_EN); // Enable the timer interrupt OS_REG_WRITE(ah, AR_IMR_S5, OS_REG_READ(ah, AR_IMR_S5) | AR_IMR_S5_GENTIMER7); OS_REG_WRITE(ah, AR_IMR, OS_REG_READ(ah, AR_IMR) | AR_IMR_GENTMR); if (clearbssid) { // If the bssid regs are set and all we want is a wake on timer, we run into an issue // with the wake coming in too early. OS_REG_WRITE(ah, AR_BSS_ID0, 0); OS_REG_WRITE(ah, AR_BSS_ID1, 0); } } /* * enable seq number generation in hw */ OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); ar5416SetPowerModeWowSleep(ah); AH_PRIVATE(ah)->ah_wow_event_mask = wow_event_mask; return (AH_TRUE); }
void ar9300_enable_cck_detect(struct ath_hal *ah) { OS_REG_RMW_FIELD(ah, AR_PHY_MODE, AR_PHY_MODE_DISABLE_CCK, 0); OS_REG_RMW_FIELD(ah, AR_PHY_MODE, AR_PHY_MODE_DYNAMIC, 1); }
void ar9300_disable_dc_offset(struct ath_hal *ah) { OS_REG_RMW_FIELD(ah, AR_PHY_TIMING2, AR_PHY_TIMING2_DC_OFFSET, 0); }
static void ar9300_classify_strong_bins(struct ath_hal *ah) { OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_CF_BIN_THRESH, 0x1); }
static HAL_BOOL ar2316SetPowerTable(struct ath_hal *ah, int16_t *minPower, int16_t *maxPower, HAL_CHANNEL_INTERNAL *chan, u_int16_t *rfXpdGain) { struct ath_hal_5212 *ahp = AH5212(ah); RAW_DATA_STRUCT_2316 *pRawDataset = AH_NULL; u_int16_t pdGainOverlap_t2; int16_t minCalPower2316_t2; u_int16_t *pdadcValues = ahp->ah_pcdacTable; u_int16_t gainBoundaries[4]; u_int32_t i, reg32, regoffset; HDPRINTF(ah, HAL_DBG_RF_PARAM, "%s:chan 0x%x flag 0x%x\n", __func__, chan->channel,chan->channelFlags); if (IS_CHAN_G(chan) || IS_CHAN_108G(chan)) pRawDataset = &ahp->ah_rawDataset2413[headerInfo11G]; else if (IS_CHAN_B(chan)) pRawDataset = &ahp->ah_rawDataset2413[headerInfo11B]; else { HDPRINTF(ah, HAL_DBG_RF_PARAM, "%s:illegal mode\n", __func__); return AH_FALSE; } pdGainOverlap_t2 = (u_int16_t) SM(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP); ar2316getGainBoundariesAndPdadcsForPowers(ah, chan->channel, pRawDataset, pdGainOverlap_t2,&minCalPower2316_t2,gainBoundaries, rfXpdGain, pdadcValues); OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, (pRawDataset->pDataPerChannel[0].numPdGains - 1)); /* * Note the pdadc table may not start at 0 dBm power, could be * negative or greater than 0. Need to offset the power * values by the amount of minPower for griffin */ if (minCalPower2316_t2 != 0) ahp->ah_txPowerIndexOffset = (int16_t)(0 - minCalPower2316_t2); else ahp->ah_txPowerIndexOffset = 0; /* Finally, write the power values into the baseband power table */ regoffset = 0x9800 + (672 <<2); /* beginning of pdadc table in griffin */ for (i = 0; i < 32; i++) { reg32 = ((pdadcValues[4*i + 0] & 0xFF) << 0) | ((pdadcValues[4*i + 1] & 0xFF) << 8) | ((pdadcValues[4*i + 2] & 0xFF) << 16) | ((pdadcValues[4*i + 3] & 0xFF) << 24) ; OS_REG_WRITE(ah, regoffset, reg32); regoffset += 4; } OS_REG_WRITE(ah, AR_PHY_TPCRG5, SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) | SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) | SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) | SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); return AH_TRUE; }
/* * Set all the beacon related bits on the h/w for stations * i.e. initializes the corresponding h/w timers; * also tells the h/w whether to anticipate PCF beacons */ void ar5211SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs) { struct ath_hal_5211 *ahp = AH5211(ah); HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: setting beacon timers\n", __func__); HALASSERT(bs->bs_intval != 0); /* if the AP will do PCF */ if (bs->bs_cfpmaxduration != 0) { /* tell the h/w that the associated AP is PCF capable */ OS_REG_WRITE(ah, AR_STA_ID1, OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PCF); /* set CFP_PERIOD(1.024ms) register */ OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod); /* set CFP_DUR(1.024ms) register to max cfp duration */ OS_REG_WRITE(ah, AR_CFP_DUR, bs->bs_cfpmaxduration); /* set TIMER2(128us) to anticipated time of next CFP */ OS_REG_WRITE(ah, AR_TIMER2, bs->bs_cfpnext << 3); } else { /* tell the h/w that the associated AP is not PCF capable */ OS_REG_WRITE(ah, AR_STA_ID1, OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_PCF); } /* * Set TIMER0(1.024ms) to the anticipated time of the next beacon. */ OS_REG_WRITE(ah, AR_TIMER0, bs->bs_nexttbtt); /* * Start the beacon timers by setting the BEACON register * to the beacon interval; also write the tim offset which * we should know by now. The code, in ar5211WriteAssocid, * also sets the tim offset once the AID is known which can * be left as such for now. */ OS_REG_WRITE(ah, AR_BEACON, (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM)) | SM(bs->bs_intval, AR_BEACON_PERIOD) | SM(bs->bs_timoffset ? bs->bs_timoffset + 4 : 0, AR_BEACON_TIM) ); /* * Configure the BMISS interrupt. Note that we * assume the caller blocks interrupts while enabling * the threshold. */ HALASSERT(bs->bs_bmissthreshold <= MS(0xffffffff, AR_RSSI_THR_BM_THR)); ahp->ah_rssiThr = (ahp->ah_rssiThr &~ AR_RSSI_THR_BM_THR) | SM(bs->bs_bmissthreshold, AR_RSSI_THR_BM_THR); OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr); /* * Set the sleep duration in 1/8 TU's. */ #define SLEEP_SLOP 3 OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLDUR, (bs->bs_sleepduration - SLEEP_SLOP) << 3); #undef SLEEP_SLOP }