示例#1
0
文件: uart.c 项目: hylu/s3c6410_ucos
void UART_CalcBaudrate( UART_REGS *pUartRegs, UART_CON *pUartCon)
{
    const u32 aSlotTable[16] = {0x0000, 0x0080, 0x0808, 0x0888, 0x2222, 0x4924, 0x4a52, 0x54aa,
                                0x5555, 0xd555, 0xd5d5, 0xddd5, 0xdddd, 0xdfdd, 0xdfdf, 0xffdf
                               };
    float tempDiv;
    u32 nOpClock;
    u32 nSlot;

    switch(pUartCon->cOpClock)
    {
    case 1 :
        nOpClock = g_uOpClock;
        break;// Uextclk
    case 3 :
        nOpClock = g_uOpClock;
        break;// Epll
    case 0 :
    case 2 : // Pclk
    default :
        nOpClock = g_PCLK;
        break;
    }

    tempDiv = (nOpClock/(16.*pUartCon->uBaudrate)) - 1;
    nSlot = (u32)((tempDiv - (int)tempDiv) * 16);
    Outp32(&pUartRegs->rUbrDiv , (u32)(tempDiv));
    Outp32(&pUartRegs->rUdivSlot , aSlotTable[nSlot]);
    //UART_Printf(" div = %d, slot = 0x%x\n", (u32)(tempDiv), aSlotTable[nSlot]);

}
/*
	Function for setting measurement period
	Parameter :
		BaseAddr = PPMU IP BASE ADDRESS
		clk_count = for caculation
*/
s32 PPMU_SetCIGCondition(addr_u32 BaseAddr, u32 eventIdx, u32 UpperThreshold, u32 UpperRepeat, u32 LowerThreshold, u32 LowerRepeat)
{
    u32 uRegValue;

    if (PPMU_GetVersion(BaseAddr) == 2) {
        uRegValue = Inp32(BaseAddr+rV2_PMNC);
        uRegValue = Inp32(BaseAddr + rV2_CIG_CFG0);

        uRegValue = uRegValue & ~(0xf<<4);
        uRegValue = uRegValue | ((LowerRepeat & 0xf)<<4);

        uRegValue = uRegValue & ~(0xf<<8);
        uRegValue = uRegValue | ((UpperRepeat & 0xf)<<8);

        uRegValue = uRegValue & ~(0x1<<16); /* Lower bound relationship : Any */
        uRegValue = uRegValue | (0x1<<20); /* Upper bound relationship : All */

        Outp32(BaseAddr + rV2_CIG_CFG0, uRegValue);

        Outp32(BaseAddr + rV2_CIG_CFG1, LowerThreshold);
        Outp32(BaseAddr + rV2_CIG_CFG2, UpperThreshold);
    } else {
        return 1;
    }
    return 0;
}
示例#3
0
文件: otp.c 项目: 1paul1/dynamite
bool otp_cmd_standby(void)
{
	u32 ulreg;
	u32 uErrorCnt = 0;
	bool bResult = false;

	/* 1. set standby command */
	ulreg = Inp32(rOTP_CON_CONRTOL);
	Outp32(rOTP_CON_CONRTOL, (ulreg & 0xfffffff7) | 0x08);

	while (true) {
		if (Inp32(rOTP_INT_STATUS) & 0x08) {
			bResult = true;
			break;
		}
		uErrorCnt++;
		if (uErrorCnt > 0xffffff) {
			bResult = false;
			break;
		}
	}

	ulreg = Inp32(rOTP_INT_STATUS);
	Outp32(rOTP_INT_STATUS, (ulreg | 0x08));

	return bResult;
}
示例#4
0
文件: otp.c 项目: 1paul1/dynamite
bool otp_cmd_init(void)
{
	u32 ulreg;
	u32 uErrorCnt = 0;
	bool bResult = false;

	Outp32(rOTP_CON_CONRTOL, 0x01);

	while (true) {
		if (Inp32(rOTP_INT_STATUS) & 0x01) {
			bResult = true;
			break;
		}
		uErrorCnt++;
		if (uErrorCnt > 0xffffff) {
			bResult = false;
			break;
		}
	}

	ulreg = Inp32(rOTP_INT_STATUS);
	Outp32(rOTP_INT_STATUS, (ulreg | 0x01));

	return bResult;
}
void bts_setotf_sysreg(BWL_SYSREG_RT_NRT_SEL path_sel, addr_u32 base, bool enable)
{
	unsigned int tmp_reg;

	tmp_reg = Inp32(base);

	if(enable)
		Outp32(base, tmp_reg | (0x1<<path_sel));
	else
		Outp32(base, tmp_reg & ~(0x1<<path_sel));
}
/*
	Function for filtering
	Parameter :
		SM_ID_V : sfr value
		SM_ID_A : sfr value
		SM_Other_V : sfr value
		SM_Other_A : sfr value
*/
s32 PPMU_Filter(addr_u32 BaseAddr, u32 SM_ID_V, u32 SM_ID_A, u32 SM_Other_V, u32 SM_Other_A)/* Just for Debugging */
{
    if (PPMU_GetVersion(BaseAddr) == 2) {
        Outp32(BaseAddr+rV2_SM_ID_V, SM_ID_V);
        Outp32(BaseAddr+rV2_SM_ID_A, SM_ID_A);
        Outp32(BaseAddr+rV2_SM_OTHERS_V, SM_ID_V);
        Outp32(BaseAddr+rV2_SM_OTHERS_A, SM_ID_A);
    } else {
        return 1;
    }
    return 0;
}
/*
	Function For Enable Interrupt
	Parameter :
		BaseAddr = PPMU IP BASE ADDRESS
*/
void PPMU_EnableOverflowInterrupt(addr_u32 BaseAddr)
{
    u32 uRegValue;

    if (PPMU_GetVersion(BaseAddr) == 2) {
        uRegValue = 0x1<<31 | 0xf; /* CCNT and All PMCNTx */
        Outp32(BaseAddr+rV2_INTENS, uRegValue);
    } else { /* must be v1.1 and not support this function. */
        uRegValue = 0x1<<31 | 0xf; /* CCNT and All PMCNTx */
        Outp32(BaseAddr+rV1_INTENS, uRegValue);
    }
}
/*
	Function for stop ppmu counting used in Auto, Manual and CIG mode
	Parameter :
		BaseAddr = PPMU IP BASE ADDRESS
*/
void PPMU_Stop(addr_u32 BaseAddr)
{
    u32 uRegValue;

    if (PPMU_GetVersion(BaseAddr) == 2) {
        uRegValue = Inp32(BaseAddr+rV2_PMNC);
        uRegValue &= ~0x1;	/* stop signal */
        Outp32(BaseAddr+rV2_PMNC, uRegValue);
    } else { /* must be v1.1 */
        uRegValue = Inp32(BaseAddr+rV1_PMNC);
        uRegValue &= ~0x1;
        Outp32(BaseAddr+rV1_PMNC, uRegValue);
    }
}
/*
	Function for changing start method to external trigger(sysreg)
	Parameter :
		BaseAddr = PPMU IP BASE ADDRESS
*/
void PPMU_ControlByExtTrigger(addr_u32 BaseAddr)/* start/stop by external trigger(or SYSCON) */
{
    u32 uRegValue;

    if (PPMU_GetVersion(BaseAddr) == 2) {
        uRegValue = Inp32(BaseAddr+rV2_PMNC);
        uRegValue |= 0x1<<16;
        Outp32(BaseAddr+rV2_PMNC, uRegValue);
    } else { /* must be v1.1 */
        uRegValue = Inp32(BaseAddr+rV1_PMNC);
        uRegValue |= 0x1<<16;
        Outp32(BaseAddr+rV1_PMNC, uRegValue);
    }
}
示例#10
0
文件: uart.c 项目: hylu/s3c6410_ucos
u32 UART_InitializeREG( UART_REGS *pUartRegs, UART_CON *pUartCon) // Initialize register set with current control set
{


#if 0
    UART_CalcBaudrate(pUartRegs, pUartCon);

    Outp32(&pUartRegs->rUfCon , (pUartCon->cTxTrig<<6)|(pUartCon->cRxTrig<<4)|TX_FIFO_RESET|RX_FIFO_RESET
           |(pUartCon->cEnableFifo));

    Outp32(&pUartRegs->rUlCon , (pUartCon->cSelUartIrda<<6)|(pUartCon->cParityBit<<3)|(pUartCon->cStopBit<<2)
           |(pUartCon->cDataBit));
    Outp32(&pUartRegs->rUCon , (pUartCon->cOpClock<<10)|TX_INT_TYPE|RX_INT_TYPE|RX_ERR_INT_EN|RX_TIMEOUT_EN
           |(pUartCon->cLoopTest<<5)| (pUartCon->cSendBreakSignal<<4) |(pUartCon->cTxMode<<2)|(pUartCon->cRxMode));
    if(pUartCon->cSendBreakSignal)
        return SENDBREAK;
//	Outp32(&pUartRegs->rUfCon , (pUartCon->cTxTrig<<6)|(pUartCon->cRxTrig<<4)|TX_FIFO_RESET|RX_FIFO_RESET
//						|(pUartCon->cEnableFifo));
    Outp32(&pUartRegs->rUmCon , (pUartCon->cRtsTrig<<5)|(pUartCon->cAfc<<4)|RTS_ACTIVE);
    Outp32(&pUartRegs->rUintM , 0xf); // mask
    Outp32(&pUartRegs->rUintSp , 0xf); // source pending clear
    Outp32(&pUartRegs->rUintP , 0xf); // pending clear
#endif
    return 0;

}
示例#11
0
文件: timer.c 项目: hylu/s3c6410_ucos
//////////
// Function Name : Isr_WDT
// Function Description : This function is Interrupt Service Routine of WatchDog Timer
// Input : NONE
// Output : NONE (increment of g_uIntCounterWT value)
// Version : v0.1
void Isr_WDT(void)
{

	Outp32(rWTCLRINT ,1);    // Watchdog timer interrupt clear 	
	g_uIntCounterWT++;
	
	UART_Printf("%d ", g_uIntCounterWT);
	 
	INTC_ClearVectAddr();    
}
/*
	Function for reset counter CCNT, PMCNTx
	Parameter :
		BaseAddr = PPMU IP BASE ADDRESS
*/
void PPMU_Reset(addr_u32 BaseAddr)
{
    u32 uRegValue;

    if (PPMU_GetVersion(BaseAddr) == 2) {
        uRegValue = Inp32(BaseAddr+rV2_PMNC);
        uRegValue |= (0x1<<2); /* 0x1: Reset CCNT */
        uRegValue |= (0x1<<1); /* 0x1: Reset PMCNTs */
        Outp32(BaseAddr+rV2_PMNC, uRegValue);

    } else { /* must be v1.1 */
        uRegValue = Inp32(BaseAddr+rV1_PMNC);
        uRegValue |= (0x1<<2); /* 0x1: Reset CCNT */
        uRegValue |= (0x1<<1); /* 0x1: Reset PMCNTs */
        Outp32(BaseAddr+rV1_PMNC, uRegValue);

        uRegValue &= ~(0x00000006);
        Outp32(BaseAddr+rV1_PMNC, uRegValue);
    }
}
示例#13
0
文件: timer.c 项目: hylu/s3c6410_ucos
void CalibrateDelay(void)
{
	u32 i, tmpDelay=100;
	u32 uPCLK_MHz=g_PCLK/1000000;
	
	delayLoopCount = 5000;
	
	Outp32(rWTCON, (uPCLK_MHz-1)<<8);
	Outp32(rWTDAT, 0xffff);						//for first update
	Outp32(rWTCNT, 0xffff);						//resolution=16us @any PCLK 
	Outp32(rWTCON, ((uPCLK_MHz-1)<<8)|(1<<5));	//Watch-dog timer start
	
	for(;tmpDelay>0;tmpDelay--)
		for(i=0;i<delayLoopCount;i++);
	
	Outp32(rWTCON, (uPCLK_MHz-1)<<8);   		//Watch-dog timer stop
	i = 0xffff - Inp32(rWTCNT);                 // 1count->16us, 100*5000 cycle runtime = 
	delayLoopCount = 50000000/(i*16);         	//100*5000:16*i[us]=1*x:100[us] -> x=50000000/(16*i)

}
示例#14
0
int board_late_init (void)
{
	unsigned int regs;
	char boot_cmd[100];

	regs = Inp32(INF_REG_BASE + INF_REG3_OFFSET);
	Outp32(0xe02002a0, 0x10000000);
	Outp32(0xe02002c0, 0x1);

	switch(regs) {
	case BOOT_NAND:
		Outp32(0xe02002a4, 0x0);	// LED0 On
		Outp32(0xe02002c4, 0x1);	// LED1 Off

         	printf("checking mode for fastboot ...\n");

         	if((~readl(0xE0200C04)) & 0x6) {
         		run_command("fastboot", 0);
                } else
		if(default_boot_mode) {		// using default environment
			sprintf(boot_cmd, "nand read %08x 600000 400000;nand read %08x B00000 300000; bootm %08x %08x"
					, MEMORY_BASE_ADDRESS + 0x8000
					, MEMORY_BASE_ADDRESS + 0x1000000
					, MEMORY_BASE_ADDRESS + 0x8000
					, MEMORY_BASE_ADDRESS + 0x1000000);
			setenv("bootcmd", boot_cmd);

			sprintf(boot_cmd, "root=ramfs devfs=mount console=ttySAC1,115200");
			setenv("bootargs", boot_cmd);
		}
		break;
	case BOOT_MMCSD:
		Outp32(0xe02002a4, 0x80);	// LED1 On
		Outp32(0xe02002c4, 0x0);	// LED0 Off

		if((~Inp32(0xe0200c04)) & 0x6) { // Linux Recovery Booting Mode
			sprintf(boot_cmd, "nand erase clean;nand scrub;movi read u-boot %08x;nand write %08x 0 70000;movi read kernel %08x;bootm %08x"
					, MEMORY_BASE_ADDRESS + 0x1000000, MEMORY_BASE_ADDRESS + 0x1000000
					, MEMORY_BASE_ADDRESS + 0x8000, MEMORY_BASE_ADDRESS + 0x8000);
			setenv("bootcmd", boot_cmd);
			sprintf(boot_cmd, "root=/dev/mmcblk0p3 rootfstype=ext3 console=ttySAC1,115200 rootdelay=1 recovery");
			setenv("bootargs", boot_cmd);
			sprintf(boot_cmd, "0");
			setenv("bootdelay", boot_cmd);
		} else
		if(default_boot_mode) {	// using default environment
			sprintf(boot_cmd, "movi read kernel %08x; bootm %08x"
					, MEMORY_BASE_ADDRESS + 0x8000
					, MEMORY_BASE_ADDRESS + 0x8000);
			setenv("bootcmd", boot_cmd);
			sprintf(boot_cmd, "root=/dev/mmcblk0p4 rootfstype=ext3 console=ttySAC1,115200 rootdelay=1");	// Android Booting Mode
			setenv("bootargs", boot_cmd);
		}
		break;
	}

	//LCD_turnon();
	return 0;
}
示例#15
0
文件: timer.c 项目: hylu/s3c6410_ucos
//////////
// Function Name : PWM_stop
// Function Description : This function stops timer individually
// Input : nNum [0:timer0   1:timer1   2:timer2   3:timer3]
// Output : NONE
// Version : v0.1
void PWM_stop(u32 uNum)
{
	u32 uTemp;

	uTemp = Inp32(rTCON);

	if(uNum == 0)
			uTemp &= ~(0x1);
	else
			uTemp &= ~((0x10)<<(uNum*4));
		
	Outp32(rTCON,uTemp);
}
/*
	Function for setting CIG Interrupt enable
	Parameter :
		BaseAddr = PPMU IP BASE ADDRESS
		PMCNTxen = enable interrupt signal for PMCNTx
*/
s32 PPMU_EnableCIGInterrupt(addr_u32 BaseAddr, u32 PMCNT0en, u32 PMCNT1en, u32 PMCNT2en)
{
    u32 uRegValue;

    if (PPMU_GetVersion(BaseAddr) == 2) {
        uRegValue = Inp32(BaseAddr+rV2_PMNC);
        uRegValue = Inp32(BaseAddr + rV2_CIG_CFG0);
        uRegValue = uRegValue | PMCNT0en | (PMCNT1en<<1) | (PMCNT2en<<2);
        Outp32(BaseAddr + rV2_CIG_CFG0, uRegValue);
    } else {
        return 1;
    }
    return 0;
}
示例#17
0
文件: timer.c 项目: hylu/s3c6410_ucos
//////////
// Function Name : Isr_TIMER3
// Function Description : This function is Interrupt Service Routine of PWM Timer0
// Input : NONE
// Output : NONE (increment of g_uIntCounter0 value)
// Version : v0.1
void Isr_TIMER3(void)
{
	u32 uTmp;
	
	uTmp = Inp32(rTINT_CSTAT);
	uTmp = (uTmp & 0x1f) | (1<<8);
	Outp32(rTINT_CSTAT,uTmp);       //  Timer3 Interrupt Clear register
    
	UART_Printf("Timer3\n");
	g_uIntCounter3++;
	
	INTC_ClearVectAddr();    

}
/*
	Function for start ppmu counting by APB signal used in Auto or Manual mode
	Parameter :
		BaseAddr = PPMU IP BASE ADDRESS
		eMode = Auto, Manual, CIG (Ref. ppmu.h)

*/
void PPMU_Start(addr_u32 BaseAddr, PPMU_MODE eMode)/* for individual control use CNTENS/C Reg */
{
    u32 uRegValue;

    if (PPMU_GetVersion(BaseAddr) == 2) {
        uRegValue = Inp32(BaseAddr+rV2_PMNC);
        uRegValue = uRegValue & ~(0x3<<20);/* clear Start Mode */
        uRegValue =
            (eMode == PPMU_MODE_MANUAL)	? uRegValue | (0x0<<20) :
            (eMode == PPMU_MODE_AUTO)	? uRegValue | (0x1<<20) :
            (eMode == PPMU_MODE_CIG)	? uRegValue | (0x2<<20) : 0;
        uRegValue |= 0x1;/* Start counting throung APB interface */

        if (eMode == PPMU_MODE_CIG)
            PPMU_SetGICMeasurementPeriod(BaseAddr, 400); /* 1000ms interval */

        Outp32(BaseAddr+rV2_PMNC, uRegValue);
    } else { /* must be v1.1 and only 'manual mode' exist. */
        uRegValue = Inp32(BaseAddr+rV1_PMNC);
        uRegValue &= ~0x1;
        uRegValue |= 0x1;
        Outp32(BaseAddr+rV1_PMNC, uRegValue);
    }
}
/*
	Function for starting with external trigger(sysreg)
	Parameter :
		BaseAddr = PPMU IP BASE ADDRESS
		controlAddr = SYSREG_PERIS ALL_PPMU_CON BaseAddr
		eMode = Auto, Menaul, CIG (Ref. ppmu.h)
*/
s32 PPMU_StartByExtTrigger(addr_u32 BaseAddr, addr_u32 controlAddr, PPMU_MODE eMode)
{

    u32 uRegValue;

    if (PPMU_GetVersion(BaseAddr) == 2) {
        if (eMode != PPMU_MODE_CIG) {
            uRegValue = Inp32(BaseAddr+rV2_PMNC);
            uRegValue = uRegValue & ~(0x3<<20);/* clear Start Mode */
            uRegValue =
                (eMode == PPMU_MODE_MANUAL)	? uRegValue | (0x0<<20) :
                (eMode == PPMU_MODE_AUTO)	? uRegValue | (0x1<<20) : 0;
            Outp32(BaseAddr+rV2_PMNC, uRegValue);

            Outp32(controlAddr, 0xFFFFFFFF); /* SYSREF PPMU External Trigger */
        } else {
            return 1;
        }
    } else { /* must be v1.1 and only 'manual mode' exist. */
        Outp32(controlAddr, 0xFFFFFFFF); /* SYSREF PPMU External Trigger */
    }

    return 0;
}
示例#20
0
文件: cf.c 项目: cyj1988jyc/2440-test
//////////
// Function Name : CF_SetMem
// Function Description : 
//   This function sets up data to specified address of memory.
// Input : eSize - size of data
//		uDstAddr - address of destination
//		uValue - data value
// Output : NONE
// Version : v0.1 
void CF_SetMem(eACCESS_SIZE eSize, u32 uDstAddr, u32 uValue)
{
	switch(eSize)
	{
		case eBYTE :
//	UART_Printf("DstAddr:0x%x, Value:0x%x\n", uDstAddr, uValue);			
			Outp8(uDstAddr, uValue);
			break;
		case eHWORD :
			Outp16(uDstAddr, uValue);
			break;
		case eWORD :
			Outp32(uDstAddr, uValue);
			break;
	}
}
/*
	Function for event setting for CCNT, PMCNT0, PMCNT1, PMCNT2, PMCNT3
	Parameter :
		BaseAddr = PPMU IP BASE ADDRESS
		eEventx = event number (Ref. ppmu.h)
*/
void PPMU_SetEvent(addr_u32 BaseAddr, PPMU_EVENT012 eEvent0, PPMU_EVENT012 eEvent1, PPMU_EVENT012 eEvent2, PPMU_EVENT3 eEvent3)
{
    u32 uRegValue;

    if (PPMU_GetVersion(BaseAddr) == 2) {
        uRegValue &= ~(0xff);
        uRegValue = (u32)eEvent0;
        Outp32(BaseAddr+rV2_CH_EV0_TYPE, uRegValue);

        uRegValue &= ~(0xff);
        uRegValue = (u32)eEvent1;
        Outp32(BaseAddr+rV2_CH_EV1_TYPE, uRegValue);

        uRegValue &= ~(0xff);
        uRegValue = (u32)eEvent2;
        Outp32(BaseAddr+rV2_CH_EV2_TYPE, uRegValue);

        uRegValue &= ~(0xff);
        uRegValue = (u32)eEvent3;
        Outp32(BaseAddr+rV2_CH_EV3_TYPE, uRegValue);
    } else { /* must be v1.1 */
        uRegValue &= ~(0xff);
        uRegValue = (u32)eEvent0;
        Outp32(BaseAddr+rV1_BEVT0SEL, uRegValue);

        uRegValue &= ~(0xff);
        uRegValue = (u32)eEvent1;
        Outp32(BaseAddr+rV1_BEVT1SEL, uRegValue);

        uRegValue &= ~(0xff);
        uRegValue = (u32)eEvent2;
        Outp32(BaseAddr+rV1_BEVT2SEL, uRegValue);

        uRegValue &= ~(0xff);
        uRegValue = (u32)eEvent3;
        Outp32(BaseAddr+rV1_BEVT3SEL, uRegValue);
    }
}
示例#22
0
文件: timer.c 项目: hylu/s3c6410_ucos
void Isr_TIMEROS(void)
{
	u32 uTmp;
	u32 uCnt;
	
	uTmp = Inp32(rTINT_CSTAT);

	for(uCnt = 0 ; uCnt <50 ; uCnt++)
	UART_Printf("#%d : rTINT_CSTAT = %x\n",uCnt,uTmp);

	
//	uTmp = (uTmp & 0x1f)| (1<<5);
	Outp32(rTINT_CSTAT,uTmp);       //  Timer0 Interrupt Clear register
    
	UART_Printf("Timer0\n");
	UART_Printf("IntCounter = %d \n ",g_uIntCounterOS);
	
	g_uIntCounterOS++;

	INTC_ClearVectAddr();

}
/*
	Function for initiating PPMU defualt setting
	Parameter :
		BaseAddr = PPMU IP BASE ADDRESS
*/
void PPMU_Init(addr_u32 BaseAddr)
{
    u32 uRegValue;
    u32  bIsCounting;

    if (PPMU_GetVersion(BaseAddr) == 2) {
        /* reset to default */
        uRegValue = Inp32(BaseAddr+rV2_PMNC);

        bIsCounting = uRegValue & 0x1;
        if (bIsCounting) {
            uRegValue &= ~(1<<0); /* counting disable */
            Outp32(BaseAddr+rV2_PMNC, uRegValue);
        }
        uRegValue = uRegValue & ~(0x3<<20);

        uRegValue &= ~(0x1<<16);/* 0x0: Configure start mode as APB interface */
        uRegValue &= ~(0x1<<3); /* 0x0: Disable clock dividing */
        uRegValue |= (0x1<<2); /* 0x1: Reset CCNT */
        uRegValue |= (0x1<<1); /* 0x1: Reset PMCNTs */
        Outp32(BaseAddr+rV2_PMNC, uRegValue);

        /* Count Enable CCNT, PMCNTTx */
        Outp32(BaseAddr+rV2_CNTENS, 0x8000000f);

        PPMU_EnableOverflowInterrupt(BaseAddr);
    } else { /* must be v1.1 */
        uRegValue = Inp32(BaseAddr+rV1_PMNC);

        bIsCounting = uRegValue & 0x1;
        if (bIsCounting) {
            uRegValue &= ~(1<<0);
            Outp32(BaseAddr+rV1_PMNC, uRegValue);
        }

        uRegValue &= ~(0x1<<3); /* NO CC Divider */
        uRegValue |= 0x1<<2; /* Reset CCNT */
        uRegValue |= 0x1<<1; /* Reset All PMCNTs */
        Outp32(BaseAddr+rV1_PMNC, uRegValue);

        Outp32(BaseAddr+rV1_CNTENS, 0x8000000f);

        PPMU_EnableOverflowInterrupt(BaseAddr);
    }
}
/*
	Function for getting result count for CIG mode
	Parameter :
		BaseAddr = PPMU IP BASE ADDRESS
		uClockcount = for clock count
		uEventxCount = for PMCNTx count
*/
s32 PPMU_GetCIGResult(addr_u32 BaseAddr, u32 *uClockCount, u32 *uEvent0Count, u32 *uEvent1Count, u32 *uEvent2Count, u64  *uEvent3Count)
{
    u32 uRegValue;

    if (PPMU_GetVersion(BaseAddr) == 2) {
        if (PPMU_GetVersion(BaseAddr) == 2) {
            /* Clear Interrupt */
            uRegValue = Inp32(BaseAddr + rV2_CIG_RESULT);

            uRegValue = uRegValue | (1<<4) | (1<<0);
            Outp32(BaseAddr + rV2_CIG_RESULT, uRegValue);

            *uClockCount = Inp32(BaseAddr+rV2_CCNT);
            *uEvent0Count = Inp32(BaseAddr+rV2_PMCNT0);
            *uEvent1Count = Inp32(BaseAddr+rV2_PMCNT1);
            *uEvent2Count = Inp32(BaseAddr+rV2_PMCNT2);
            *uEvent3Count = (u64)(Inp32(BaseAddr+rV2_PMCNT3_LOW)) + (((u64)(Inp32(BaseAddr+rV2_PMCNT3_HIGH)&0xff))<<32);
        }
    } else {
        return 1;
    }
    return 0;
}
示例#25
0
文件: timer.c 项目: hylu/s3c6410_ucos
void WDT_operate(u32 uEnReset, u32 uEnInt, u32 uSelectCLK, u32 uEnWDT, u32 uPrescaler,u32 uWTDAT, u32 uWTCNT)
{

	float fWDTclk;


	
	Outp32(rWTCON,0);
	Outp32(rWTDAT,0);
	Outp32(rWTCNT,0);
	Outp32(rWTDAT,uWTDAT);
	Outp32(rWTCNT,uWTCNT);
	Outp32(rWTCON,(uEnReset<<0)|(uEnInt<<2)|(uSelectCLK<<3)|(uEnWDT<<5)|((uPrescaler)<<8));

	fWDTclk = (1/(float)((float)g_PCLK/((float)uPrescaler+1)/(1<<(uSelectCLK+4))))*uWTDAT;
	UART_Printf("WDT_clk = %f sec\n",fWDTclk);


}
/*
	Function for deinitializing ppmu
	Parameter :
		BaseAddr = PPMU IP BASE ADDRESS
*/
void PPMU_DeInit(addr_u32 BaseAddr)
{
    if (PPMU_GetVersion(BaseAddr) == 2) {
        /* clear */
        Outp32(BaseAddr+rV2_FLAG, (0x1<<31 | 0xf));
        Outp32(BaseAddr+rV2_INTENC, (0x1<<31 | 0xf));
        Outp32(BaseAddr+rV2_CNTENC, (0x1<<31 | 0xf));
        Outp32(BaseAddr+rV2_CNT_RESET, (1<<31)|0xf);

        /* reset to default */
        Outp32(BaseAddr+rV2_PMNC, 0x0);
        Outp32(BaseAddr+rV2_CIG_CFG0, 0x0);
        Outp32(BaseAddr+rV2_CIG_CFG1, 0x0);
        Outp32(BaseAddr+rV2_CIG_CFG2, 0x0);
        Outp32(BaseAddr+rV2_CNT_AUTO, 0x0);
        Outp32(BaseAddr+rV2_PMCNT0, 0x0);
        Outp32(BaseAddr+rV2_PMCNT1, 0x0);
        Outp32(BaseAddr+rV2_PMCNT2, 0x0);
        Outp32(BaseAddr+rV2_PMCNT3_LOW, 0x0);
        Outp32(BaseAddr+rV2_PMCNT3_HIGH, 0x0);
        Outp32(BaseAddr+rV2_CCNT, 0x0);
        Outp32(BaseAddr+rV2_CH_EV0_TYPE, 0x0);
        Outp32(BaseAddr+rV2_CH_EV1_TYPE, 0x0);
        Outp32(BaseAddr+rV2_CH_EV2_TYPE, 0x0);
        Outp32(BaseAddr+rV2_CH_EV3_TYPE, 0x0);
        Outp32(BaseAddr+rV2_SM_ID_V, 0x0);
        Outp32(BaseAddr+rV2_SM_ID_A, 0x0);
        Outp32(BaseAddr+rV2_SM_OTHERS_V, 0x0);
        Outp32(BaseAddr+rV2_SM_OTHERS_A, 0x0);
        Outp32(BaseAddr+rV2_INTERRUPT_TEST, 0x0);

    } else { /* must be v1.1 */
        Outp32(BaseAddr+rV1_INTENC, (0x1<<31 | 0xf));
        Outp32(BaseAddr+rV1_CNTENC, (0x1<<31 | 0xf));
        Outp32(BaseAddr+rV1_COUNTER_RESET, (0x3<<16) | (0xf<<0));
        Outp32(BaseAddr+rV1_PMNC, 0x0);
        Outp32(BaseAddr+rV1_CNTENS, 0x0);
    }
}
void bts_setmo_sysreg(BWL_MO_SYSREG_IP mo_id, addr_u32 base, unsigned int ar_mo,
			unsigned int aw_mo)
{
	unsigned int tmp_reg;

	switch (mo_id) {
		case BTS_SYSREG_ISP1_M0:
			tmp_reg = Inp32(base + ISP_XIU_ISP1_AR_AC_TARGET_CON) & ~(0x3F<<16);
			/* reset value(0xC), [19:16] for AR */
			Outp32(base + ISP_XIU_ISP1_AR_AC_TARGET_CON, tmp_reg | ((ar_mo&0x3F)<<16));
			tmp_reg = Inp32(base + ISP_XIU_ISP1_AW_AC_TARGET_CON) & ~(0x3F<<16);
			/* reset value(0xC), [21:16] for AW */
			Outp32(base + ISP_XIU_ISP1_AW_AC_TARGET_CON, tmp_reg | ((aw_mo&0x3F)<<16));
			break;
		case BTS_SYSREG_ISP1_S1:
			tmp_reg = Inp32(base + ISP_XIU_ISP1_AR_AC_TARGET_CON) & ~(0x3F<<8);
			/* reset value(0x4), [10:8] for AR */
			Outp32(base + ISP_XIU_ISP1_AR_AC_TARGET_CON, tmp_reg | ((ar_mo&0x3F)<<8));
			tmp_reg = Inp32(base + ISP_XIU_ISP1_AW_AC_TARGET_CON) & ~(0x3F<<8);
			/* reset value(0x8), [11:8] for AW */
			Outp32(base + ISP_XIU_ISP1_AW_AC_TARGET_CON, tmp_reg | ((aw_mo&0x3F)<<8));
			break;
		case BTS_SYSREG_ISP1_S0:
			tmp_reg = Inp32(base + ISP_XIU_ISP1_AR_AC_TARGET_CON) & ~(0x3F);
			/* reset value(0x8), [3:0] for AR */
			Outp32(base + ISP_XIU_ISP1_AR_AC_TARGET_CON, tmp_reg | (ar_mo&0x3F));
			tmp_reg = Inp32(base + ISP_XIU_ISP1_AW_AC_TARGET_CON) & ~(0x3F);
			/* reset value(0x18), [4:0] for AW */
			Outp32(base + ISP_XIU_ISP1_AW_AC_TARGET_CON, tmp_reg | (aw_mo&0x3F));
			break;
		case BTS_SYSREG_ISP0_M0:
			tmp_reg = Inp32(base + ISP_XIU_ISP0_AR_AC_TARGET_CON) & ~(0x3F<<24);
			/* reset value(0x8), [27:24] for AR */
			Outp32(base + ISP_XIU_ISP0_AR_AC_TARGET_CON, tmp_reg | ((ar_mo&0x3F)<<24));
			tmp_reg = Inp32(base + ISP_XIU_ISP0_AW_AC_TARGET_CON) & ~(0x3F<<24);
			/* reset value(0x8), [28:24] for AW */
			Outp32(base + ISP_XIU_ISP0_AW_AC_TARGET_CON, tmp_reg | ((aw_mo&0x3F)<<24));
			break;
		case BTS_SYSREG_ISP0_S2:
			tmp_reg = Inp32(base + ISP_XIU_ISP0_AR_AC_TARGET_CON) & ~(0x3F<<16);
			/* reset value(0x1), [16:16] for AR */
			Outp32(base + ISP_XIU_ISP0_AR_AC_TARGET_CON, tmp_reg | ((ar_mo&0x3F)<<16));
			tmp_reg = Inp32(base + ISP_XIU_ISP0_AW_AC_TARGET_CON) & ~(0x3F<<16);
			/* reset value(0x1), [19:16] for AW */
			Outp32(base + ISP_XIU_ISP0_AW_AC_TARGET_CON, tmp_reg | ((aw_mo&0x3F)<<16));
			break;
		case BTS_SYSREG_ISP0_S1:
			tmp_reg = Inp32(base + ISP_XIU_ISP0_AR_AC_TARGET_CON) & ~(0x3F<<8);
			/* reset value(0x8), [11:8] for AR */
			Outp32(base + ISP_XIU_ISP0_AR_AC_TARGET_CON, tmp_reg | ((ar_mo&0x3F)<<8));
			tmp_reg = Inp32(base + ISP_XIU_ISP0_AW_AC_TARGET_CON) & ~(0x3F<<8);
			/* reset value(0x8), [11:8] for AW */
			Outp32(base + ISP_XIU_ISP0_AW_AC_TARGET_CON, tmp_reg | ((aw_mo&0x3F)<<8));
			break;
		case BTS_SYSREG_ISP0_S0:
			tmp_reg = Inp32(base + ISP_XIU_ISP0_AR_AC_TARGET_CON) & ~(0x3F);
			/* reset value(0x1), [0:0] for AR */
			Outp32(base + ISP_XIU_ISP0_AR_AC_TARGET_CON, tmp_reg | (ar_mo&0x3F));
			tmp_reg = Inp32(base + ISP_XIU_ISP0_AW_AC_TARGET_CON) & ~(0x3F);
			/* reset value(0x8), [3:0] for AW */
			Outp32(base + ISP_XIU_ISP0_AW_AC_TARGET_CON, tmp_reg | (aw_mo&0x3F));
			break;
		default:
			break;
	}
}
void bts_setqos_sysreg(BWL_QOS_SYSREG_IP qos_id, addr_u32 base, unsigned int ar_qos,
			unsigned int aw_qos)
{
	unsigned int tmp_val;
	aw_qos = aw_qos&0xF;
	ar_qos = ar_qos&0xF;

	switch (qos_id) {
		case BTS_SYSREG_AUD:
			Outp32(base + DISPAUD_XIU_DISPAUD_QOS_CON, (aw_qos<<16)|(ar_qos<<12)|\
				(Inp32(base + DISPAUD_XIU_DISPAUD_QOS_CON)&0xFFF00FFF));
			break;
		case BTS_SYSREG_DISP:
			Outp32(base + DISPAUD_QOS_SEL, 0x0); /* DISP Qos select : 0x0(SYSREG QOS), 0x1(DECON QOS) */
			Outp32(base + DISPAUD_XIU_DISPAUD_QOS_CON, (ar_qos<<8)|(ar_qos<<4)|(ar_qos)|\
				(Inp32(base + DISPAUD_XIU_DISPAUD_QOS_CON)&0xFFFFF000));
			break;
		case BTS_SYSREG_FSYS0:
			Outp32(base + FSYS_QOS_CON0, (aw_qos<<28)|(ar_qos<<24)| \
				(aw_qos<<12)|(ar_qos<<8)|(aw_qos<<4)|(ar_qos));
			break;
		case BTS_SYSREG_FSYS1:
			Outp32(base + FSYS_QOS_CON1, (aw_qos<<20)|(ar_qos<<16)| \
				(aw_qos<<12)|(ar_qos<<8)|(aw_qos<<4)| \
				(ar_qos));
			break;
		case BTS_SYSREG_IMEM:
			Outp32(base + IMEM_QOS_CON, (ar_qos<<16)|(aw_qos<<12)| \
				(ar_qos<<8)|(aw_qos<<4)|(ar_qos));
			break;
		case BTS_SYSREG_FIMC_SCL:
			Outp32(base + ISP_QOS_CON0, (aw_qos<<28)| \
				(Inp32(base + ISP_QOS_CON0)&0x0FFFFFFF));
			break;
		case BTS_SYSREG_FIMC_FD:
			Outp32(base + ISP_QOS_CON0, (aw_qos<<20)|(ar_qos<<16)| \
				(Inp32(base + ISP_QOS_CON0)&0xFF00FFFF));
			break;
		case BTS_SYSREG_FIMC_ISP:
			Outp32(base + ISP_QOS_CON0, (aw_qos<<12)|(ar_qos<<8)| \
				(Inp32(base + ISP_QOS_CON0)&0xFFFF00FF));
			break;
		case BTS_SYSREG_FIMC_BNS_L:
			Outp32(base + ISP_QOS_CON0, (aw_qos<<4)| \
				(Inp32(base + ISP_QOS_CON0)&0xFFFFFF0F));
			break;
		case BTS_SYSREG_MIF_MODAPIF:
			tmp_val = 0x1;/* MODEM Qos select : 0x0(SYSREG QOS), 0x1(MODEM QOS) */
			Outp32(base + MIF_MODAPIF_QOS_CON, (aw_qos<<8)|(ar_qos<<4)|tmp_val);
			break;
		case BTS_SYSREG_MIF_CPU:
			Outp32(base + MIF_CPU_QOS_CON, (aw_qos<<4)|ar_qos);
			break;
		case BTS_SYSREG_MFC:
			Outp32(base + MFCMSCL_QOS_CON, (aw_qos<<28)|(ar_qos<<24)| \
				(Inp32(base + MFCMSCL_QOS_CON)&0x00FFFFFF));
			break;
		case BTS_SYSREG_JPEG:
			Outp32(base + MFCMSCL_QOS_CON, (aw_qos<<20)|(ar_qos<<16)| \
				(Inp32(base + MFCMSCL_QOS_CON)&0xFF00FFFF));
			break;
		case BTS_SYSREG_MSCL:
			Outp32(base + MFCMSCL_QOS_CON, (aw_qos<<12)|(ar_qos<<8)| \
				(aw_qos<<4)|(ar_qos)| \
				(Inp32(base + MFCMSCL_QOS_CON)&0xFFFF0000));
			break;
		default:
			break;
	}
}
/*
	Function for setting measurement period
	Parameter :
		BaseAddr = PPMU IP BASE ADDRESS
		clk_count = for caculation
*/
void PPMU_SetGICMeasurementPeriod(addr_u32 BaseAddr, u32 clk_count)
{
    u32 uRegValue = 0xFFFFFFFF - (clk_count*1024*1024-1);
    Outp32(BaseAddr+rV2_CCNT, uRegValue); /* 1000ms interval */
}
/*
	Function for stopping with external trigger(sysreg)
	Parameter :
		controlAddr = SYSREG_PERIS ALL_PPMU_CON BaseAddr
*/
void PPMU_StopByExtTrigger(addr_u32 controlAddr)
{
    Outp32(controlAddr, 0x0);
}