/*---------------------------------------------------------------------------------------*/ VOID OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly ) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; VOID *BrazosPciePortPtr; VOID *BrazosPcieDdiPtr; ALLOCATE_HEAP_PARAMS AllocHeapParams; PCIe_PORT_DESCRIPTOR PortList [] = { // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) { 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0) }, #if 1 // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0) }, // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) { 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0) }, // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) }, #endif // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) } }; PCIe_DDI_DESCRIPTOR DdiList [] = { // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) { 0, //Descriptor flags PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) {ConnectorTypeDP, Aux1, Hdp1} }, // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) { DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) {ConnectorTypeDP, Aux2, Hdp2} } }; PCIe_COMPLEX_DESCRIPTOR Brazos = { DESCRIPTOR_TERMINATE_LIST, 0, &PortList[0], &DdiList[0] }; // GNB PCIe topology Porting // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); if ( Status!= AGESA_SUCCESS) { // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR ASSERT(FALSE); return; } BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; AllocHeapParams.BufferPtr += sizeof(Brazos); BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; AllocHeapParams.BufferPtr += sizeof(PortList); BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemFill (BrazosPcieComplexListPtr, 0, sizeof(Brazos), &InitEarly->StdHeader); LibAmdMemFill (BrazosPciePortPtr, 0, sizeof(PortList), &InitEarly->StdHeader); LibAmdMemFill (BrazosPcieDdiPtr, 0, sizeof(DdiList), &InitEarly->StdHeader); LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader); LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; }
* 31 DP1_TX[P,N]3 * 32 DP2_TX[P,N]0 * 33 DP2_TX[P,N]1 * 34 DP2_TX[P,N]2 * 35 DP2_TX[P,N]3 * 36 DP2_TX[P,N]4 * 37 DP2_TX[P,N]5 * 38 DP2_TX[P,N]6 */ PCIe_PORT_DESCRIPTOR PortList [] = { /* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */ { 0, /* Descriptor flags */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, /* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */ { 0, /* Descriptor flags */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, /* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */ { DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) }, };
*/ #include "PlatformGnbPcieComplex.h" #include <string.h> #include <northbridge/amd/agesa/agesawrapper.h> #include <vendorcode/amd/agesa/f12/Proc/CPU/heapManager.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...) { 0, //Descriptor flags PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT2) }, // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...) { 0, //Descriptor flags PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT3) }, // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) { 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) }, // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) {
* GNU General Public License for more details. */ #include <AGESA.h> #include <PlatformMemoryConfiguration.h> #include <northbridge/amd/agesa/state_machine.h> static const PCIe_PORT_DESCRIPTOR PortList[] = { // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0) }, // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0) }, // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) {
static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) { AGESA_STATUS Status; void *BrazosPcieComplexListPtr; void *BrazosPciePortPtr; void *BrazosPcieDdiPtr; ALLOCATE_HEAP_PARAMS AllocHeapParams; /** * @brief Initialize Port descriptors */ PCIe_PORT_DESCRIPTOR PortList [] = { /* (PCIe port, Lanes 4, PCI Device Number 4, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) }, /* (PCIe port, Lanes 5, PCI Device Number 5, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) }, /* (PCIe port, Lanes 6, PCI Device Number 6, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) }, /* (PCIe port, Lanes 7, PCI Device Number 7, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) }, /* (PCIe port, Lanes 8, PCI Device Number 8, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) } }; /** * @brief Initialize Ddi descriptors */ PCIe_DDI_DESCRIPTOR DdiList [] = { /* (DDI interface Lanes 8:11, DdA, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), /* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) */ {ConnectorTypeLvds, Aux1, Hdp1} }, /* (DDI interface Lanes 12:15, DdB, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), /* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) */ {ConnectorTypeDP, Aux2, Hdp2} } }; PCIe_COMPLEX_DESCRIPTOR Brazos = { DESCRIPTOR_TERMINATE_LIST, 0, &PortList[0], &DdiList[0] }; /** * @brief GNB PCIe topology Porting * * Allocate buffer for * PCIe_COMPLEX_DESCRIPTOR, PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); ASSERT(Status == AGESA_SUCCESS); BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; AllocHeapParams.BufferPtr += sizeof(Brazos); BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *) AllocHeapParams.BufferPtr; AllocHeapParams.BufferPtr += sizeof(PortList); BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList)); ((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR *) BrazosPciePortPtr; ((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR *) BrazosPcieDdiPtr; InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; return AGESA_SUCCESS; }
* @param[in] Engine Standard configuration header. * @retval Native PHY lane bitmap */ UINT32 PcieGetNativePhyLaneBitmapTN ( IN UINT32 PhyLaneBitmap, IN PCIe_ENGINE_CONFIG *Engine ) { return PhyLaneBitmap; } STATIC PCIe_PORT_DESCRIPTOR DefaultSbPortTN = { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeLowLoss, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmL0sL1, 0) }; /*----------------------------------------------------------------------------------------*/ /** * Build default SB configuration descriptor * * * @param[in] SocketId Socket Id * @param[out] SbPort Pointer to SB configuration descriptor * @param[in] StdHeader Standard configuration header. * @retval AGESA_SUCCESS Configuration data build successfully */ AGESA_STATUS PcieGetSbConfigInfoTN ( IN UINT8 SocketId,