/*******************************************************************************
* mvPciArbEnable - PCI arbiter enable/disable
*
* DESCRIPTION:
* This fuction enable/disables a given PCI interface arbiter.
* NOTE: Arbiter setting can not be changed while in work. It should only
* be set once.
* INPUT:
* pciIf - PCI interface number.
* enable - Enable/disable parameter. If enable = MV_TRUE then enable.
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable)
{
MV_U32 regVal;
/* Parameter checking */
if (pciIf >= mvCtrlPciMaxIfGet())
{
mvOsPrintf("mvPciArbEnable: ERR. Invalid PCI interface %d\n", pciIf);
return MV_ERROR;
}
/* Set PCI Arbiter Control register according to default configuration */
regVal = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf));
/* Make sure arbiter disabled before changing its values */
MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE);
regVal &= ~PCI_ARBITER_CTRL_DEFAULT_MASK;
regVal |= PCI_ARBITER_CTRL_DEFAULT; /* Set default configuration */
if (MV_TRUE == enable)
{
regVal |= PACR_ARB_ENABLE;
}
else
{
regVal &= ~PACR_ARB_ENABLE;
}
/* Write to register */
MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), regVal);
return MV_OK;
}
/*******************************************************************************
* mvPciArbParkDis - Disable arbiter parking on agent
*
* DESCRIPTION:
* This function disables the PCI arbiter from parking on the given agent
* list.
*
* INPUT:
* pciIf - PCI interface number.
* pciAgentMask - When a bit in the mask is set to '1', parking on
* the associated PCI master is disabled. Mask bit
* refers to bit 0 - 6. For example disable parking on PCI
* agent 3 set pciAgentMask 0x4 (bit 3 is set).
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask)
{
MV_U32 pciArbiterCtrl;
/* Parameter checking */
if (pciIf >= mvCtrlPciMaxIfGet())
{
mvOsPrintf("mvPciArbParkDis: ERR. Invalid PCI interface %d\n", pciIf);
return MV_ERROR;
}
/* Reading Arbiter Control register */
pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf));
/* Arbiter must be disabled before changing parking */
MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE);
/* do the change */
pciArbiterCtrl &= ~PACR_PARK_DIS_MASK;
pciArbiterCtrl |= (pciAgentMask << PACR_PARK_DIS_OFFS);
/* writing new value ( if th earbiter was enabled before the change */
/* here it will be reenabled */
MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl);
return MV_OK;
}
/*******************************************************************************
* mvPciArbBrokDetectSet - Set PCI arbiter broken detection
*
* DESCRIPTION:
* This function sets the maximum number of cycles that the arbiter
* waits for a PCI master to respond to its grant assertion. If a
* PCI agent fails to respond within this time, the PCI arbiter aborts
* the transaction and performs a new arbitration cycle.
* NOTE: Value must be greater than '1' for conventional PCI and
* greater than '5' for PCI-X.
*
* INPUT:
* pciIf - PCI interface number.
* pClkCycles - Number of PCI clock cycles. If equal to '0' the broken
* master detection is disabled.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
*
*******************************************************************************/
MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles)
{
MV_U32 pciArbiterCtrl;
MV_U32 pciMode;
/* Parameter checking */
if (pciIf >= mvCtrlPciMaxIfGet())
{
mvOsPrintf("mvPciArbBrokDetectSet: ERR. Invalid PCI interface %d\n",
pciIf);
return MV_BAD_PARAM;
}
/* Checking PCI mode and if pClkCycles is legal value */
pciMode = MV_REG_READ(PCI_MODE_REG(pciIf));
pciMode &= PMR_PCI_MODE_MASK;
if (PMR_PCI_MODE_CONV == pciMode)
{
if (pClkCycles < PACR_BROKEN_VAL_CONV_MIN)
return MV_ERROR;
}
else
{
if (pClkCycles < PACR_BROKEN_VAL_PCIX_MIN)
return MV_ERROR;
}
pClkCycles <<= PACR_BROKEN_VAL_OFFS;
/* Reading Arbiter Control register */
pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf));
pciArbiterCtrl &= ~PACR_BROKEN_VAL_MASK;
pciArbiterCtrl |= pClkCycles;
/* Arbiter must be disabled before changing broken detection */
MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE);
/* writing new value ( if th earbiter was enabled before the change */
/* here it will be reenabled */
MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl);
return MV_OK;
}
/*******************************************************************************
* mvBoardIdGet - Get Board model
*
* DESCRIPTION:
* This function returns board ID.
* Board ID is 32bit word constructed of board model (16bit) and
* board revision (16bit) in the following way: 0xMMMMRRRR.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* 32bit board ID number, '-1' if board is undefined.
*
*******************************************************************************/
MV_U32 mvBoardIdGet(MV_VOID)
{
MV_U32 tmpBoardId = -1;
BOARD_DATA boardData;
if(gBoardId != -1)
return gBoardId;
#if defined(MV_88F1181)
if(boardEepromGet(&boardData) == MV_OK)
{
tmpBoardId = (MV_U32)boardData.boardId;
}
else
{
/* until we have relevant data in twsi then we
will detect the board type from sdram config reg */
if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2)
{
tmpBoardId = DB_88F1181_DDR2;
}
else
{
tmpBoardId = DB_88F1181_DDR1;
}
}
#elif defined(MV_88F5181)
if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2)
{
}
else /* DDR1 */
{
#if defined(RD_88F5182)
tmpBoardId = RD_88F5182_2XSATA;
#elif defined(RD_88F5182_3)
tmpBoardId = RD_88F5182_2XSATA3;
#elif defined(RD_88W8660)
tmpBoardId = RD_88W8660_DDR1;
#elif defined(RD_88F5181L_FE)
tmpBoardId = RD_88F5181L_VOIP_FE;
#elif defined(RD_88F5181L_GE)
tmpBoardId = RD_88F5181L_VOIP_GE;
#elif defined(MV_POS_NAS)
tmpBoardId = RD_88F5181_POS_NAS;
#elif defined(MV_VOIP)
tmpBoardId = RD_88F5181_VOIP;
#elif defined(DB_PRPMC)
tmpBoardId = DB_88F5181_DDR1_PRPMC;
#elif defined(DB_PEX_PCI)
tmpBoardId = DB_88F5181_DDR1_PEXPCI;
#else
tmpBoardId = RD_88F5181_POS_NAS;
#endif
}
if(tmpBoardId != -1) {
gBoardId = tmpBoardId;
return tmpBoardId;
}
//jack20060626
// if(boardEepromGet(&boardData) == MV_OK)
// {
// tmpBoardId = (MV_U32)boardData.boardId;
// }
// else
{
/* until we have relevant data in twsi then we
will detect the board type from sdram config reg */
if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2)
{
if((mvCtrlModelGet() == MV_5281_DEV_ID)&&(mvCtrlRevGet() >= 0x1))
{
tmpBoardId = DB_88F5X81_DDR2;
}
else if(mvCtrlModelGet() == MV_8660_DEV_ID)
{
tmpBoardId = DB_88W8660_DDR2;
}
else if(mvCtrlModelGet() == MV_5182_DEV_ID)
{
tmpBoardId = DB_88F5182_DDR2;
}
else
{
tmpBoardId = DB_88F5181_5281_DDR2;
}
}
else /* DDR1 */
{
if (MV_REG_READ(PCI_ARBITER_CTRL_REG(0)) & PACR_ARB_ENABLE) /* arbiter enabled*/
{
if((mvCtrlModelGet() == MV_5281_DEV_ID)&&(mvCtrlRevGet() >= 0x1))
{
tmpBoardId = DB_88F5X81_DDR1;
}
else
{
tmpBoardId = DB_88F5181_5281_DDR1;
}
}
else /* arbiter disabled */
{
if ((MV_REG_READ(PEX_CTRL_REG(0)) & PXCR_DEV_TYPE_CTRL_MASK)
== PXCR_DEV_TYPE_CTRL_CMPLX) /*root complex*/
{
tmpBoardId = DB_88F5181_DDR1_PRPMC;
}
else if ((MV_REG_READ(PEX_CTRL_REG(0)) & PXCR_DEV_TYPE_CTRL_MASK)
== PXCR_DEV_TYPE_CTRL_POINT) /*end point*/
{
tmpBoardId = DB_88F5181_DDR1_PEXPCI;
}
}
}
}
gBoardId = tmpBoardId;
return tmpBoardId;
#else
# error "CHIP not selected"
#endif
}
