static int
mpc83xx_indirect_write_config(struct pci_bus *bus, unsigned int devfn,
int offset, int len, u32 val)
{
struct pci_controller *hose = bus->sysdata;
volatile unsigned char *cfg_data;
u8 cfg_type = 0;
u8 bus_num;
if (ppc_md.pci_exclude_device)
if (ppc_md.pci_exclude_device(bus->number, devfn))
return PCIBIOS_DEVICE_NOT_FOUND;
if (bus->number == hose->first_busno)
bus_num = 0;
else
bus_num = bus->number;
PCI_CFG_OUT(hose->cfg_addr,
(0x80000000 | (bus_num << 16)
| (devfn << 8) | ((offset & 0xfc) | cfg_type)));
/*
* Note: the caller has already checked that offset is
* suitably aligned and that len is 1, 2 or 4.
*/
cfg_data = hose->cfg_data + (offset & 3);
switch (len) {
case 1:
out_8((u8 *)cfg_data, val);
break;
case 2:
out_le16((u16 *)cfg_data, val);
break;
default:
out_le32((u32 *)cfg_data, val);
break;
}
return PCIBIOS_SUCCESSFUL;
}
static int
indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
int len, u32 *val)
{
struct pci_controller *hose = bus->sysdata;
volatile void __iomem *cfg_data;
u8 cfg_type = 0;
if (ppc_md.pci_exclude_device)
if (ppc_md.pci_exclude_device(bus->number, devfn))
return PCIBIOS_DEVICE_NOT_FOUND;
if (hose->set_cfg_type)
if (bus->number != hose->first_busno)
cfg_type = 1;
PCI_CFG_OUT(hose->cfg_addr,
(0x80000000 | ((bus->number - hose->bus_offset) << 16)
| (devfn << 8) | ((offset & 0xfc) | cfg_type)));
/*
* Note: the caller has already checked that offset is
* suitably aligned and that len is 1, 2 or 4.
*/
cfg_data = hose->cfg_data + (offset & 3);
switch (len) {
case 1:
*val = in_8(cfg_data);
break;
case 2:
*val = in_le16(cfg_data);
break;
default:
*val = in_le32(cfg_data);
break;
}
return PCIBIOS_SUCCESSFUL;
}
static void __init sequoia_setup_pci(void)
{
void *pci_reg_base;
void *pci_cfg_base;
unsigned long memory_size;
memory_size = ppc_md.find_end_of_memory();
pci_reg_base = ioremap64(SEQUOIA_PCIL0_BASE, SEQUOIA_PCIL0_SIZE);
pci_cfg_base = ioremap64(SEQUOIA_PCI_CFGREGS_BASE, 64);
PCI_CFG_OUT(SEQUOIA_PCI_CFGA_OFFSET,
0x80000000 | (PCI_COMMAND & 0xfc));
PCI_CFG_OUT(SEQUOIA_PCI_CFGD_OFFSET,
( PCI_CFG_IN(SEQUOIA_PCI_CFGD_OFFSET) |
PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER));
/* Disable region first */
PCI_WRITEL(0, SEQUOIA_PCIL0_PMM0MA);
/* PLB starting addr: 0x0000000180000000 */
PCI_WRITEL(SEQUOIA_PCI_PHY_MEM_BASE, SEQUOIA_PCIL0_PMM0LA);
/* PCI start addr, 0x80000000 (PCI Address) */
PCI_WRITEL(SEQUOIA_PCI_MEM_BASE, SEQUOIA_PCIL0_PMM0PCILA);
PCI_WRITEL(0, SEQUOIA_PCIL0_PMM0PCIHA);
/* Enable no pre-fetch, enable region */
PCI_WRITEL(((0xffffffff -
(SEQUOIA_PCI_UPPER_MEM - SEQUOIA_PCI_MEM_BASE)) | 0x01),
SEQUOIA_PCIL0_PMM0MA);
/* Disable region one */
PCI_WRITEL(0, SEQUOIA_PCIL0_PMM1MA);
PCI_WRITEL(0, SEQUOIA_PCIL0_PMM1LA);
PCI_WRITEL(0, SEQUOIA_PCIL0_PMM1PCILA);
PCI_WRITEL(0, SEQUOIA_PCIL0_PMM1PCIHA);
PCI_WRITEL(0, SEQUOIA_PCIL0_PMM1MA);
/* Disable region two */
PCI_WRITEL(0, SEQUOIA_PCIL0_PMM2MA);
PCI_WRITEL(0, SEQUOIA_PCIL0_PMM2LA);
PCI_WRITEL(0, SEQUOIA_PCIL0_PMM2PCILA);
PCI_WRITEL(0, SEQUOIA_PCIL0_PMM2PCIHA);
PCI_WRITEL(0, SEQUOIA_PCIL0_PMM2MA);
/* Now configure the PCI->PLB windows, we only use PTM1
*
* For Inbound flow, set the window size to all available memory
* This is required because if size is smaller,
* then Eth/PCI DD would fail as PCI card not able to access
* the memory allocated by DD.
*/
PCI_WRITEL(0, SEQUOIA_PCIL0_PTM1MS); /* disabled region 1 */
PCI_WRITEL(0, SEQUOIA_PCIL0_PTM1LA); /* begin of address map */
memory_size = 1 << fls(memory_size - 1);
/* Size low + Enabled */
PCI_WRITEL((0xffffffff - (memory_size - 1)) | 0x1, SEQUOIA_PCIL0_PTM1MS);
eieio();
iounmap(pci_reg_base);
}
